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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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High-Gain Double-Bulk Mixer in 65 nm CMOS with 830 ${\mu}W$ Power Consumption

  • Schweiger, Kurt (Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology) ;
  • Zimmermann, Horst (Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology)
  • Received : 2009.12.18
  • Accepted : 2010.02.10
  • Published : 2010.06.30
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Abstract

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

Keywords

References

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