An Interleaved Five-level Boost Converter with Voltage-Balance Control

Abstract

This paper proposes an interleaved five-level boost converter based on a switched-capacitor network. The operating principle of the converter under the CCM mode is analyzed. A high voltage gain, low component stress, small input current ripple, and self-balancing function for the capacitor voltages in the switched-capacitor networks are achieved. In addition, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop has been researched to achieve good performances and voltage-balance effect. An experimental study has been done to verify the correctness and feasibility of the proposed converter and control strategy.

I. INTRODUCTION

It is well known that two-stage two-level energy conversion systems composed of a two-level dc-dc converter and a two-level dc-ac inverter, as shown in Fig. 1, are usually utilized in low-voltage applications of less than 1kV. When working on medium-voltage applications with 2.4kV or 3.3kV and megawatt capacity, the two-stage system may not be competent [1]-[3].

Fig.1The two-stage two-level energy conversion system.

Over the past three years, a two-stage multilevel energy conversion system with a novel control method has been developed for wind power generation systems, which output medium-voltage levels [4]-[7]. As shown in Fig. 2, the two-stage multilevel energy conversion system is composed of a multilevel dc-dc converter and a multilevel dc-ac inverter. It can also be seen that they share the same dc link capacitors. Owing to the multilevel structure, the system can operate at relatively low switching frequencies and use fast low voltage devices. More importantly, the dc link capacitors can be controlled by the former multilevel dc-dc converter instead of the latter multilevel inverter, which simplifies the control scheme for the latter multilevel inverter. To achieve a small size and a high power density, non-isolated multilevel dc-dc converters are better than isolated multilevel dc-dc converters. In addition, the presence of a high voltage gain and a small ripple are both welcome.

Fig.2The two-stage multilevel energy conversion system.

The authors of [8] proposed a multilevel boost converter (MBC) based on voltage multipliers, which has a high voltage gain and a self-balance function for capacitor voltages. In addition, this function can be advantageous for balancing the dc link capacitor voltages as shown in Fig. 2 [9,10]. An interleaved multilevel boost converter based on a MBC is proposed to reduce input current ripple [11]. However, more components are necessary, which makes this a poor choice. New four-level and a five-level boost converters together with their corresponding modulation strategies have been proposed in [12]-[14]. However, the voltage gains of these converters are not high. Another possible solution is the application of a diode-capacitor voltage multiplier on classical non-isolated dc-dc converters [15]-[17]. These converters exhibit high voltage gains and low voltage stress. However, the input current ripple is very high since no interleaved schemes are adopted. Recently, switched-capacitor techniques have been researched and applied to medium-voltage and high-power dc-dc converters, and good performance has been achieved [18]-[20].

In the paper, a five-level boost converter based on a switched-capacitor technique is proposed. This paper is organized as follows: Section II introduces the operation principles of the converter under the CCM mode. A three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop, is proposed to solve the neutral-point potential imbalance issue in Section III. Experimental verifications are presented in Section IV. Finally, some conclusion are drawn at the last section.

 

II. THE PROPOSED CONVERTER

The three-level boost converter shown in Fig. 3(a) has been widely used in renewable generation applications. However, it cannot be used in high voltage applications since its output level is limited to three. The five-level boost converter shown in Fig. 3(b) was proposed in [14]. Since it can output five voltage levels, the voltage stresses across the components are smaller than those of the three-level boost converter. However, both converters show low voltage gains and the five-level boost converter has many switches with a complex voltage-balance control strategy since four capacitor voltages are sampled and controlled.

Fig. 3.Multilevel boost converter.

According to the above analysis, a five-level boost converter is proposed based on the switched-capacitor network in Fig. 4. The two switched-capacitor networks are labelled as switched-capacitor I and switched-capacitor II. The switches S1 and S2 are controlled by two different drive signals, which are phase-shift 180 degrees with the same duty cycle d. Equivalent circuits of the converter are presented in Fig. 5 and typical waveforms are given in Fig. 6. To ensure balanced capacitor voltages, all of the capacitors have the same capacitance and two switches. In addition, all of the diodes have the same parameters.

Fig. 4.The proposed five-level boost converter based on switched-capacitor network.

Fig. 5.Equivalent circuits. (a) Stage I. (b) Stage II. (c) Stage III. (d) Stage IV.

Fig. 6.Typical waveforms: (a) d>0.5; (b) d≤0.5.

Stage I: when S1 and S2 are both turned on, D2 and D5 are forwarded while D1, D3, D4 and D6 are reverse-biased, as shown in Fig. 5(a). During this period, the inductor L is charged by the input source Uin. If UC1 is smaller than UC4, then UC4 clamps UC1 through S1 and D2. If UC2 is smaller than UC5, then UC5 clamps UC2 through S2 and D5. Therefore, the following expressions can be given:

Stage II: when S1 is turned on while S2 is turned off, D2, D4 and D6 are forwarded while D1, D3 and D5 are reverse-biased, shown in Fig. 5(b). During this period, C5 is charged by L and Uin through S1 and D4. Additionally, UC4 clamps UC1 through S1 and D2, which meets for (2). C5 and C6 are charged by Uin, L and UC2 through S1 and D6. Thus, some expressions can be given:

It can be derived from (4) and (5) that:

Stage III: when S1 is turned off while S2 is turned on, D2, D4 and D6 are reverse-biased while D1, D3 and D5 are forwarded, as shown in Fig. 5(c). During this period, C4 is charged by L and Uin through S2 and D1. In addition, UC5 clamps UC2 through S2 and D5, which meets for (3). C3 and C4 are charged by Uin, L and UC1 through S2 and D3. Thus, some expressions can be given:

It can be derived from (7) and (8) that:

Stage IV: when S1 and S2 are both turned off, D1, D3, D4 and D6 are forwarded while D2 and D5 are reverse-biased, as shown in Fig. 5(d). During this period, C3 and C4 are connected in series to be charged by L and Uin through D1 and D4. In addition, C3, C4, C5 and C6 are charged by Uin, L, UC1 and UC2 through D3 and D6. Thus, there is:

In all of these stages, the output voltage can be obtained by the accumulation of four capacitor voltages as follows:

When the duty cycle d is bigger than 0.5, the converter operates in the stages I, II, I and III; and when d is smaller than 0.5, it operates in the stages IV, II, IV and III. No matter what d is, the same output results can be achieved according to (1)-(12):

In addition, all of the capacitor voltages can be achieved:

 

III. VOLTAGE-BALANCE CONTROL

As analyzed in Section II, the proposed converter has a self-balance function for some of the capacitor voltages due to the switched-capacitor technique. UC1, UC3 and UC4 are self-balanced with one uniform voltage level, while UC2, UC5 and UC6 are self-balanced with another uniform voltage level. To make the two different voltage levels balanced, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop is proposed, as shown in Fig. 7.

Fig. 7.Three-loop control strategy.

The outer voltage loop is adopted to keep the output voltage stable and the inner current loop is adopted to improve the dynamic performance of the converter. More importantly, the voltage-balance loop is used to make the two different voltage levels balanced. That is to say, all of the capacitor voltages can be equalized by the voltage-balance loop. It should be noted that the two carrier signals Ca1 and Ca2 in Fig. 7 are phase-shifted 180 degrees to implement the interleaved scheme for S1 and S2.

Uo* and IL* represents the reference output voltage and the reference inductor current, respectively. The goal of the outer voltage loop and the inner current loop is to get the duty cycle d1 of S1. In addition, a difference duty cycle Δd is achieved through the PI controller by a difference voltage ΔU. Then, the duty cycle d2 of S2 can be easily obtained as follows:

Two definitions are given as follows:

Therefore, the voltage-balance process is: when U1 is bigger than U2, Δd becomes negative, which makes d2 a little smaller than d1. That is to say, the turn-on time of S1 is a little larger than that of S2, which makes the charging time of C5 a little larger than that of C4. Thus, U2 increases while U1 decreases. Finally U2 is equal to U1 after several switching periods. In addition, when U1 is smaller than U2, the same result can be achieved based on a similar voltage-balance process. Since the output capacitor voltages are balanced, the proposed five-level boost converter is a good choice to connect with five-level or three-level diode-clamped inverters.

 

IV. PERFORMANCE ANALYSIS

A. Performance

According to (13)-(15), it is clear that a high voltage gain and small capacitor voltages can be achieved with the proposed converter. In addition, it can be seen that the voltage stresses across all of the switches and diodes are equal to the capacitor voltages, which are just a quarter of the output voltage. Additionally, according to (2), (3), (6) and (9), it can be concluded that C1, C3 and C4 are balanced with a uniform voltage level and that C2, C5 and C6 are balanced with another uniform voltage level. The balanced process is called the self-balance function. In addition, the proposed converter is similar to a three-level boost converter. Thus, UC4 is commonly not equal to UC5, which makes the two uniform voltage levels different in practical applications. It behaves as the neutral-point potential imbalance issue. However, the two uniform voltage levels can be equalized with a simple voltage-balance loop, which has been presented in Section III.

Additionally, the inductor current ripple is:

B. Condition for the CCM

The CCM occurs when the average inductor current is bigger than the peak inductor current ripple:

The integration of (13), (14) and (19) into (20) yields the following condition for the DCM operation mode when the duty cycle d is bigger than 0.5:

Where the dimensionless parameter K is defined as follows:

In addition, the coefficient Kcrit can be expressed as follows:

When d is bigger than 0.5, the maximum value of Kcrit is 0.0046 at d=2/3. When d is smaller than 0.5, the maximum value of Kcrit is 0.012 at d =0.211. On the whole, the maximum value of Kcrit for the proposed converter should be:

Then, if it is necessary to let the proposed converter operate in the CCM mode, the result will be achieved based on (21) and (24) as follows:

(25) can be further simplified as:

(26) is an important guide to make the converter operate under the CCM mode.

C. Comparative Analysis

The proposed five-level boost converter in Fig. 4 is similar to the five-level boost converter in Fig. 3(b). A comparative analysis between the two converters is listed in Table I. In this table, G represents the voltage gain and Uvp represents the voltage stress.

TABLE ICOMPARISON ANALYSIS

According to Table I, although two more capacitors are added, the voltage gain increases from 1/(1-d) to 2/(1-d) with the same voltage stress and small input current ripple. Therefore, a low and wide input voltage range can be realized with the proposed converter. In addition, only two drive circuits are necessary for Fig. 4 since only two switches are necessary. However, four drive circuits are necessary for Fig. 3(b).

In addition, since the two switched-capacitor networks in Fig. 4 have the self-balance function for the capacitor voltages, only two capacitor voltages U1 and U2 should be sampled and controlled. On the whole, the neutral-point potential control strategy is easy to implement. However, for the five-level boost converter in Fig. 3(b), it is difficult to realize the neutral-point potential control strategy because four capacitor voltages UC3, UC4, UC5 and UC6 need to be sampled and controlled. In addition, when the capacitances of the four capacitors are different, it is more difficult to make them balanced.

 

V. EXPERIMENTAL VERIFICATION

In the experimental part, a prototype with a small output power, presented in Fig. 8, is built to verify the feasibility of the proposed converter. The experimental parameters are presented in Table II and the experimental study has been done under the CCM mode. According to (26), the inductance of L can be calculated as follows:

Fig. 8.Experimental setup.

TABLE.IIEXPERIMENTAL PARAMETERS

According to (27), if the inductance of L is bigger than 120uH, the converter operates under the CCM mode. In this paper, the inductance of L is selected to be about 508uH.

Key experimental waveforms of the converter under different input voltages are presented in Fig. 9, including waveforms of the driven signals, inductor current and output voltage. Voltage waveforms for all of the switches and diodes under an input voltage of 36V are presented in Fig. 10. In addition, dynamic experimental waveforms of the converter when the input voltage varies and the output voltage varies are presented in Fig. 11. Furthermore, the voltage-balance results are presented in Fig. 12. Meanwhile, the voltage-balance results when C3 and C4 are changed to 47uF while C5 and C6 are still 470uF are presented in Fig. 13. Finally, the conversion efficiency curves of the converter under different input voltages are also given in Fig. 14.

Fig. 9.Key experimental waveforms: (a)Uin=36V; (b) Uin=60V; (c) Uin=80V; (d) Uin=100V.

Fig. 10.Voltage waveforms of the switches and diodes under the input voltage 36V: (a) uS1, uD1, uD2, uD3; (b) uS2, uD4, uD5, uD6; (c) UC1, UC3, UC4; (d) UC2, UC5, UC6.

Fig. 11.Dynamic waveforms. (a) The input voltage increases from 36V to 59V and then decreases to 41V. (b) The output referring voltage increases from 100V to 300V and then decreases to 100V.

Fig. 12.Waveforms of the output capacitor voltages under the input voltage 36V. (a) Without voltage-balance control. (b) With voltage-balance control.

Fig. 13.Voltage-balance process under different input voltages.

Fig. 14.Conversion efficiency curve.

It should be noted that S1 and S2 are given to present the drive signals, and uS1 and uS2 are defined to describe the electric potential difference between the drain terminal and the source terminal of the switches S1 and S2. In addition, uDi (i=1, 2, 3, 4, 5, 6) are defined to describe the electric potential difference between the cathode terminal and the anode terminal of the diodes D1-D6.

As can be seen from Fig. 9, the output voltage is stable at 300V under different input voltages. The input current is continuous with a small current ripple, and the ripple frequency 40kHz is two times the switching frequency 20kHz. Moreover, when the input voltage is 80V, the duty cycles of S1 and S2 are both about 0.50, which makes the input current ripple nearly equal to zero. This can be verified by Fig. 9(c). More importantly, it is clear from Fig. 10 that the voltage stresses for all of the switches, diodes and capacitors in the converter are about 75V, which is only a quarter of the output voltage 300V. It should be noted that the six capacitors C1-C6 in the converter have nearly the same capacitor voltage. However, some voltage differences exist due to the voltage drops of the devices.

On the other hand, the converter can still output a stable voltage when the input voltage varies suddenly, as shown in Fig. 11(a). In addition, the input average current varies to make the converter achieve a steady output power. In Fig. 11(b), the output voltage increases and then decreases according to variations of the referring output voltage. In addition, the duty cycles and the average input current change like the output voltage, since the load is invariant. Fig. 12 shows that the capacitor voltages of C1, C2, C3, C4, C5 and C6 can be nearly equalized with a uniform voltage level when the voltage-balance loop is considered in the closed-loop control strategy. In Fig. 13, when C3 and C4 are changed to 47uF, the voltages of C3 and C4 are about 15V, while the voltages of C5 and C6 are about 135V. However, when the voltage-balance loop is added, they are all balanced with the same voltage level 75V.

All of these experimental results basically match with the theoretical analysis in section II and III, which demonstrates that the proposed converter is feasible. In addition, it can be seen from Fig.14 that the maximum conversion efficiency of the proposed converter is 89.9% with a 36V input voltage, 92.6% with a 60V input voltage, and 93.8% with both 80V and 100V input voltages. Furthermore, it is not difficult to conclude from Fig.14 that the larger the input voltage is, the larger the conversion efficiency becomes. This is due to the fact that when the input voltage is very low, a very high input current is produced to make the converter achieve a stable output power. However, a high input current increases the losses of the inductor, the switches and the diodes due to the presence of parasitic resistance, forward voltage drops and other non-idealities.

 

VI. CONCLUSION

This paper introduces a five-level boost converter, which can increase the input voltage to a high voltage level, attain a low component voltage stress, and achieve a small input current ripple. The operating principle of the converter under the CCM mode and the performances are analyzed. A three-loop control strategy has been presented to solve the neutral-point potential imbalance issue. In addition to good stable and dynamic performances, the capacitor voltages can be easily balanced due to the self-balance function of the two switched-capacitor networks and the voltage-balance loop. Finally, experimental results verify the correctness and feasibility of the proposed converter and control strategy.