• Journal of the Korean Vacuum Society
• /
• v.17 no.2
• /
• pp.156-159
• /
• 2008

The electrical characteristic of SiGe-on-SOI (SGOI) wafer with different Ge concentration were evaluated by pseudo-MOSFET. Epitaxial SiGe layers was grown directly on top of SOI with Ge concentrations of 16.2, 29.7, 34.3 and 56.5 at.%. As Ge concentration increased, leakage current increased and threshold voltage shifted from 3 V to 7 V in nMOSFET, from -7 V to -6 V in pMOSFET. The interface states between buried oxide and top of Si was significantly increased by the rapid thermal annealing (RTA) process, and so the electrical characteristic of SGOI wafer degraded. On the other hand, additional post RTA　annealing (PRA) showed that it was effective in decreasing the interface states generated by RTA processes and the electrical characteristic of SGOI wafer enhanced higher than initial state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.95-95
• /
• 2008

본 연구에서는 SiGe p-MOSFET을 제작하여 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성을 측정하였다. Si 기판위에 성장한 $Si_{0.88}Ge_{0.12}$으로 제작된 SiGe p-MOSFET의 채널은 게이트 산화막과 20nm 정도의 Si Spacer 층으로 분리되어 있다. 게이트 산화막은 열산화에 의해 70$\AA$으로 성장되었고, 게이트 폭은 $25{\mu}m$, 게이트와 소스/드레인 사이의 거리는 2.5때로 제작되었다. 제작된 SiGe p-MOSFET은 빠른 동작 특성, 선형성, 저주파 노이즈 특성이 우수하였다. 제작된 SiGe p-MOSFET의 ESD 에 대한 소자의 신뢰성과 내성을 연구하기 위하여 SiGe P-MOSFET에 ESD를 lkV에서 8kV까지 lkV 간격으로 가한 후, SiGe P-MOSFET의 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성 변화를 분석 비교하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.05a
• /
• pp.682-684
• /
• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics over the temperature range of 300K and 77K. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.3
• /
• pp.474-477
• /
• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics over the temperature range or 300K and 77K. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.101-102
• /
• 2009

SGOI MOSFETs with various Ge mole fractions were fabricated and compared to the SOI MOSFET. SGOI MOSFETs have a lager drain current and higher effective mobility than the SOI MOSFET as increased Ge mole fractions. The lattice constant difference causes lattice mismatch between the SiGe layer and the top-Si layer during the top-Si layer growth. However, SGOI MOSFETs have a lager leakage current at subthreshold region. Also, leakage current at subthreshold region increased with Ge mole fractions. This is attributable to the crystalline defects due to the lattice mismatch between the SiGe layer and the top-Si layer.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.3
• /
• pp.45-50
• /
• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.773-776
• /
• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.1-7
• /
• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.21-22
• /
• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• ETRI Journal
• /
• v.25 no.3
• /
• pp.203-209
• /
• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.