• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.6
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• pp.16-24
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• 1974

In this paper the method of constructing short and open stable voltage inversion negative immittance converter (VNIC) circuits is proposed according to simplified equivalent models witch consist of a parameter control circuit, and a voltage or a current control circuit. VNIC characteristics can be obtained as gate voltage of common gate connection is controlled by the output of the parameter control circuit corresponding to its input. Constructed circuits are analysed, and the experimental results are compared and cheeked with the calculated results. Errors are found less than 11%. Oscillation behavior of constructed VNIC oscillator is compared with that of negative resistance oscillator.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.815-818
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• 1998

The Insulated Gate Bipolar Transistor has the characteristics of MOSFET and BJT. The characteristics of proposed device exhibit high speed switching, the voltage controlled property, and the low ON resistance. This hybrid device has been used and developed continuously in the power electronic engineering field. We can simulate many IGBT circuits, such as the motor drive circuit, the switching circuits etc, with PSpice. However, some problems in PSpice is that the IGBT is old-fashioned and is very difficult to get it. In this paper, the IGBT in PSpice is considered as the basic structure. We changed the valuse of base width, gate-drain overlaping area, device area, and doping concentration, then calculated MOS transconductance, ambipolar recombination lifetime etc. Using this resultant parameter, we could predict the transient response characteristicsof IGBT, for examplex, voltage overshoot, the rising curve of voltage, and the falling curve of current.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1501-1502
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• 2011

In this paper, an investigation of the 8" process for Trench Power MOSFET Application and Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.283-285
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• 2001

In this paper, a new lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n+ cathode region. The improvement of latch-up performance is verified using the two-dimensional simulator MEDICI and the simulation results on the latch-up current density are 3.12${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the proposed LIGBT and 0.94${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.251-258
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• 1994

To apply the Power MOSFET to the high powerd circuits, the parallel operation of the Power MOSFET must be considered because of their low power rating. This means, in practical applications, design methods for the parallel operations are required. However, it is very difficult to investigate the problem of parallel operations by directly changing the internal parameters of the MOSFET. Thus, in this paper, the effects of internal parameters for the parallel operation are investigated using SPICE program which is often used and known that the program is very reliable. The investigation results show that while the gate resistance and gate capacitances are the parameters which affect to the dynamic switching operations, the drain and source resistances are the parameters which affect to the steady-state current unbalances. Through this investigation, the design methods for the parallel operation of the MOSFET are suggested, which, in turn, contributes to the practical use of Power MOSFETs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.65-70
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• 1994

GaAs power MESFETs with 0.8$\mu$m gate lengths are fabricated using image reversal (IR) methods on the wafer with an undoped surface layer grown by MOCVD. The fabricated GaAs power MESFETs with an undoped surface layer show that an ideality factor 1.17, a built-in potential 0.83 V, a pinch-off voltage -2.7 V, a specfic contact resistance 1.21$\times$10$^{5}$ ~3.42$\times$10$^{2}$$\Omega$-cm$^{2}$ and an extrinsic g$_{m}$ = 103.5 mS/mm. The maximum RF output power densities of the 0.8$\mu$m devices are 360 mW/mm and 499 mW/mm, and power added efficiencies 29.67% and 29.05%, for the unit gate width 150$\mu$m and 200$\mu$m at 12 GHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.38-43
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• 1994

GaAs and AlGaAs layers were grown by Molecular Beam Epitaxy (MBE) to fabricate hith performance GaAs MESFETs. Optimum growth temperatures were found to be 600$^{\circ}C$ from their Hall measurement data. MESFETs with the gate legth of 1${\mu}$m and the gate width of 100.mu.m were fabricated on the MBE-grown GaAs layters which has i-GaAs buffer layer and characterized. Knee volgate and mazimum transconductance of the devices were 1V, 224mS/mm, respectively. Cut-off frequency at on-wafer measuring pattern was measured to be 18 GHz. The MESFET with the 1${\mu}$m -thick i-Al$_{0.3}Ga_{0.7}$As buffer layer between nactive and i-GaAs was fabricated on order to reduce the leakage current which flows through the i-GaAs buffer layer. Its output resistance was 2.26 k${\Omega}$.mm which increased by a factor of 15 compared with the MESFET without i-Al$_{0.3}Ga_{0.7}$As buffer layer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.5
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• pp.29-34
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• 1977

Using JFET and bipolar transistor, we have designed a circuit of current controlled negative resitance and analysed this circuit in the operating region. Since the positive gate voltage of N-channel JFET is applied in full operating region, the output and transfer characteristics of JFET are measured in the positive gate region. The performances of this circuit are predicted from these characteristics and experimental results of the proposed CCNR circuit are presented.

• ETRI Journal
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• v.17 no.2
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.569-575
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• 2013

An improved non-quasi-static gate-source impedance model including a parallel RC block for short-channel MOSFETs is developed to simulate RF MOSFET input characteristics accurately in the wide range of high frequency. The non-quasi-static model parameters are accurately determined using the physical input equivalent circuit. This improved model results in much better agreements between the measured and modelled input impedance than a simple one with a non-quasi-static resistance up to 40GHz, verifying its accuracy.