• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.63-68
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• 2003

The DC and RF characteristics of $In_{0.5}Ga_{0.5}P/In_{0.22}Ga_{0.78}As/GaAs$ p-HEMTs with a gate oxide layer of various thicknesses ($50{\;}{\AA},{\;}300{\;}{\AA}$) were investigated and compared with those of a Schottky-gate p-HEMT without the gate oxide layer. A prominent improvement in the breakdown voltage characteristics were observed for a p-HEMT having a gate oxide layer, which was implemented by using a liquid phase oxidation technique. The on-state breakdown voltage of the p-HEMT having the oxide layer of $50{\;}{\AA}$was ~2.3 times greater than that of a Schottky-gate p-HEMT. However, the p-HEMT having the gate oxide layer of $300{\;}{\AA}$ suffered from a poor gate-control capability due to the drain induced barrier lowering (DIBL) resulting from the thick gate oxide inspite of the lower gate leakage current and the higher on-state breakdown voltage. The results for a primitive p-HEMT having the gate oxide layer without any optimization of the structure and the process indicate the potential of p-HEMT having the gate oxide layer for high-power applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.74-75
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• 2008

TIGBT has some merits which are lower on-state voltage drop and smaller cell pitch, but also has a defect which is relatively lower breakdown voltage in comparison with planar IGBT. This lower breakdown voltage is due to the electric field which is concentrated on beneath the vertical gate. Therefore in this paper, new trench IGBT structure is proposed to improve breakdown voltage In the new proposed structure, a narrow oxide beneath the trench gate edge where the electric field is concentrated is extended into rectangular shape to decrease the electric field. As a result, breakdown voltage is improved to 23%.

• 한국정보통신학회논문지
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• 제17권2호
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• pp.372-377
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• 2013

DGMOSFET의 항복전압에 대하여 고찰하였으며 이를 위하여 포아송방정식의 분석학적 해 및 Fulop의 항복전압 조건을 사용하였다. DGMOSFET는 게이트단자의 전류제어능력 향상으로 단채널 효과를 감소시킬 수 있다는 장점이 있다. 그러나 단채널에서 나타나는 항복전압의 감소는 피할 수 없으므로 이에 대한 연구가 필요하다. 포아송방정식을 풀 때 사용하는 전하분포함수에 가우시안 함수를 적용함으로써 보다 실험값에 가깝게 해석하였으며 이때 이중게이트 MOSFET의 소자크기에 따라 항복전압의 변화를 관찰하였다. 본 연구의 전위모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 항복전압을 분석할 것이다. DGMOSFET의 항복전압을 관찰한 결과, 채널길이가 감소할수록 그리고 도핑농도가 증가할수록 항복전압이 감소하는 것으로 나타났다. 또한 게이트산화막 두께 및 채널두께에 따라서 항복전압의 변화가 관찰되었다.

• 한국정보통신학회논문지
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• 제22권1호
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• pp.117-124
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• 2018

박막 두께가 다른 무접합 비정질 InGaZnO 막막 트랜지스터를 제작하고 박막 두께, 동작 온도 및 빛의 세기에 따른 소자의 성능 변수를 추출하고 게이트 산화층 항복전압을 분석하였다. 박막의 두께가 클수록 소자의 성능이 우수하나 드레인 전류의 증가로 게이트 산화층 항복전압은 감소하였다. 고온에서도 소자의 성능은 개선되었으나 게이트 산화층 항복 전압은 감소하였다. 빛의 세기가 증가할수록 광자에 의해 생성된 전자로 드레인 전류는 증가 하였으나 역시 게이트 산화층 항복전압은 감소하였다. 박의 두께가 클수록, 고온일수록, 빛의 세기가 강할수록 채널의 전자수가 증가하여 산화층으로 많이 주입되었기 때문이다. 무접합 a-IGZO 트랜지스터를 BEOL 트랜지스터로 사용하기 위해서는 박막 두께 및 동작 온도를 고려해서 산화층 두께를 설정해야 됨을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제10권6호
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• pp.193-195
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• 2009

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.200-204
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• 2012

This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.

• 한국전기전자재료학회논문지
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• 제16권12호
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 대한전자공학회논문지SD
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• 제41권8호
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• pp.1-8
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• 2004

두께가 3nm인 게이트 산화막을 사용한 n-MOSFET에 정전압 스트레스를 가하였을 때 관찰되는 SILC 및 soft breakdown 열화 및 이러한 열화가 소자 특성에 미치는 영향에 대해 실험하였다. 열화 현상은 인가되는 게이트 전압의 극성에 따라 그 특성이 다르게 나타났다. 게이트 전압이 (-)일 때 열화는 계면 및 산화막내 전하 결함에 의해 발생되었지만, 게이트 전압이 (＋)일 때는 열화는 주로 계면 결함에 의해 발생되었다. 또한 이러한 결함의 생성은 Si-H 결합의 파괴에 의해 발생할 수 있다는 것을 중수소 열처리 및 추가 수소 열처리 실험으로부터 발견하였다. OFF 전류 및 여러 가지 MOSFET의 전기적 특성의 변화는 관찰된 결함 전하(charge-trapping)의 생성과 직접적인 관련이 있다. 그러므로 실험 결과들로부터 게이트 산화막으로 터널링되는 전자나 정공에 의한 Si 및 O의 결합 파괴가 게이트 산화막 열화의 원인이 된다고 판단된다. 이러한 물리적 해석은 기존의 Anode-Hole Injection 모델과 Hydrogen-Released 모델의 내용을 모두 포함하게 된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.