• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.490-493
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• 2002

In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.690-692
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• 2003

In this paper, we have investigated characteristics of radio frequency for double gate MOSFET with 50nm main gate in according to variation of side gate length. We could know the increasement of cut-off frequency as the side gate length is lower. As a result, we could know the most optimum performance characteristics when side gate length was 70nm. In this time, the DG MOSFET of side gate with 70nm has very high cut-off frequency like 41.4GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.777-779
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• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.439-442
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• 1990

GaAs MESFETs with the submicron gat are fabricated. $G_{m,mas}$ = 195mS/mm with the $0.5{\mu}m$ gate length and $G_{m,mas}$ = 170mS/mm with the $0.6{\mu}m$ gate lenth. $f_{mas}$ = 7GHz with the $1.5{\mu}m$ gate length and the $120{\mu}m$ gate width. We can estimate that $f_{mas}$ = 15GHz with $0.6{\mu}m$ gate length and that $f_{mas}$ = 18 ${\sim}$ 20GHz with the $0.5{\mu}m$ gate length.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.6
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• pp.246-250
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• 2005

The forward voltage drop of IGBT is studied numerically and analytically as a function of gate length. An analytical expression is presented for the first time for the surface potential variation along the channel layer under the gate of IGBT. The surface potential drop and the carrier density near the surface allow calculation of the forward voltage drop of IGBT analytically as a function of the gate length. The voltage-drop in the drift region near the gate decreases exponentially, whereas that on the surface increases linearly with increasing the gate length, the sum of which exhibits an optimum gate length, resulting in a minimum forward voltage drop. Based on the surface potential drop, a remodelling of the forward voltage drop of IGBT is also proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.661-663
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• 2004

In this paper, we have investigated characteristics of C-V for double gate MOSFET with main gate and side gate by the variation of side sate length and side gate voltage. Main gate voltage is changed from -5V to +5V. We know that characteristics of C-V is good under the condition of LSG=70nm, VSG=3V, VD=2V. We have analyze characteristics of device by ISE-TCAD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.693-695
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• 2003

In this paper, we have investigated temperature-dependent characteristics of current-voltage for double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated the temperature-dependent characteristics of current-voltage and drain voltage is changed from 0V to 5.0V at $V_{mg}$ =1.5V and $V_{sg}$ =3.0V. We have obtained a very good characteristics of current-voltage for 77K. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.61-64
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• 1994

The NMOSFET with gate length of 0.1$\mu$m is fabricated by mix-and-match method. In this device, the electron beam lithography is used to form the gate layer, while other layers are formed by the stepper. The gate oxide is 7nm thick, and the device structure is normal LDD structure. The saturation Gm for gate length of 0.1$\mu$m is 246mS/mm. The subthreshold slope is 180mV/decade for 0.1$\mu$m gate length, but the slope is 80mV/decade for 0.3$\mu$m gate length.