• Transactions on Electrical and Electronic Materials
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• 제17권1호
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• pp.50-55
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• 2016

In this paper, we have analyzed the electrical characteristics of 1200V trench gate field stop IGBT and have compared to NPT planar type IGBT and NPT planar field stop IGBT. As a result of analyzing, we obtained superior electrical characteristics of trench gate field stop IGBT than conventional IGBT. To begin with, the breakdown voltage characteristic was showed 1,460 V and on state voltage drop was showed 0.7 V. We obtained 3.5 V threshold voltage, too. To use these results, we have extracted optimal design and process parameter and designed trench gate field stop IGBT. The designed trench gate IGBT will use to inverter of renewable energy and automotive industry.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.266-269
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• 2012

The most recently IGBT (insulated gate bipolar mode transistor) devices are in the most current conduction capable devices and designed to the big switching power device. Use this number of the devices are need to high voltage and low on-state voltage drop. And then in this paper design of field stop IGBT is insert N buffer layer structure in NPT planar IGBT and optimization design of field stop IGBT and trench field stop IGBT, both devices have a comparative analysis and reflection of the electrical characteristics. As a simulation result, trench field stop IGBT is electrical characteristics better than field stop IGBT.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.773-776
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• 2003

본 논문에서는 p형 SiGe pMOSFET를 디자인하고 온도에 따른 전기적 특성들을 분석하였다. 채널 길이는 0.9$\mu\textrm{m}$로 하였으며, 온도는 300K와 77K일 때의 특성을 조사하였다. 게이트 전압이 -1.5V로 인가되었을 때, 실온에서는 -0.97V의 문턱전압 값을 얻었으나 77K에서는 -1.15V의 문턱전압 값을 얻었다. 이것은 실온에서의 Si pMOSFET가 갖는 문턱전압 값(-1.36V)보다 동작특성이 우수함을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1606-1608
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• 2002

The triac is a bidirectional triode with blocking and conducting characteristics used in motor control or heater power control. This greatly simplifies the circuits required for the control of the full wave AC Power by reducing the number of power handling components and by reducing the size and complexity of the gate control circuit.[3] In this paper, We can understand measurement results of analysis which have been made on the electrical characteristics of triac with gate diffusion time for the gate area.

• 한국농공학회논문집
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• 제47권6호
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• pp.15-24
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• 2005

The normalization on the characteristics of water level change at the upstream gauging station was attempted according to the operation of drainage sluice gate of the Geumgang estuary dam. The characteristics were normalized by the analysis of water level change and by the linear-regression of the water level data measured at the inner station of Geumgang estuary dam and upstream gauging station. The results of normalization may be referred to the management of Geumgang estuary lake, the operation of pumping and drainage stations in the shore of the lake. The mean response time of water level change on Ibpo, Ganggyeong and Gyuam water level station were 39,81 and 160 minutes, when sluice gate was opened respectively. The mean velocity of surface wave, the mean displacement of water level change, the mean time of water level change and the mean rate of water level change varied largely depending on the location of gauging station and the characteristics of stream section of the water level gauging station.

• 전자공학회논문지D
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• 제34D권9호
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• pp.56-63
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• 1997

There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.118-122
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• 2009

Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator

• 전기전자학회논문지
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• 제25권1호
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• pp.1-9
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• 2021

본 논문에서는 고전압, 고전류 동작에 적합한 4H-SiC UMOSFET에 대해서 연구하였다. 일반적으로 SiO2는 SiC MOSFET에서 gate dielectric으로 가장 많이 사용되는 물질이다. 하지만 4H-SiC보다 유전 상수 값이 2.5배 낮아서 높은 전계를 갖게 되므로 SiO2/SiC 접합 부분에서 열악한 특성을 갖는다. 따라서 high-k 물질을 gate dielectric으로 적용한 소자를 SiO2를 적용한 소자와 TCAD 시뮬레이션을 통해 전기적 특성을 비교하였다. 그 결과 BV 감소, VTH 감소, gm 증가, Ron 감소를 확인하였다. 특히 온도가 300K일 때, Al2O3와 HfO2의 Ron은 66.29%, 69.49%가 감소하였으며 600K일 때도 39.71%, 49.88%가 감소하였다. 따라서 Al2O3와 HfO2가 고전압 SiC MOSFET의 gate dielectric 물질로써 적합함을 확인하였다.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.