• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1292-1294
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• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1074-1078
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator U .WOSFET have the main gate length of %m and the side gate length of 70nm. Then, u'e have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nano scale.

• Transactions on Electrical and Electronic Materials
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• v.7 no.2
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• pp.53-57
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• 2006

In this paper, a Symmetric Dual-gate Single-Si TFT, which includes three split floating n+ zones, is simulated. This structure drastically reduces the kink-effect and improves the on-current. This is due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region. This structure allows effective reduction in the kink-effect, depending on thy length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate voltages. This result shows an 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to a conventional single-gate TFT and the reduction of the output conductance in the saturation region, is observed. In addition, the reduction in hole concentration, in the channel region, in order for effectively reducing the kink-effect, is also confirmed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.99-102
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• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate signal delay, feed-through voltage and image sticking. To improve these problems which are caused by the fried-through voltage, we have evaluated new driving methods to reduce the fled-through voltage. Two level gate-pulse was used for the gate driving of the cst-on-common structure pixels. And two-gate line driving methods with the optimized gate signals were applied for the cst-on-gate structure pixels. These gate driving methods were better feed-through characteristics than conventional simple gate pulse. The evaluation of the suggested driving methods were performed by using a TFT-LCD array simulator PDAST which can simulate the gate, data and pixel voltages of a certain pixel at any time and at any location on a TFT array. The effect of the new driving method was effectively analyzed.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.1
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• pp.93.2-93.2
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• 2012

Point Spread Function (PSF) is one of the most important optical characteristics for describing the performance of a telescope. And a concept of subpixelization is inevitable in evaluating the undersampled PSF (Shin and Sakurai 2009). Then, the internal structure of Yohkoh SXT CCD pixel is not uniform: For the top half of pixel area, the X-ray should pass a so-called gate structure where the charges are transferred to an output amplifier. This gate structure shows energy-dependent sensitivity (Tsuneta et al. 1991). For example, for Al-K (8.34 A) X-ray emission, the transmission of the polysilicon gate is about 0.9. Also, for the peak coronal response of the SXT thin filters, around 17 angstrom (0.729 keV), the transmission of the gate is about 0.6, falling off sharply towards longer wavelengths. It should be noted that this spectrally dependent non-uniform response of each CCD pixel will certainly have a noticeable effect on the properties of the PSF at longer wavelengths. Therefore, especially for analyzing the undersampled PSF of low energy source, a careful consideration of non-uniform internal pixel structure is required in determining the shape of the PSF core. The details on the effect of gate structure will be introduced in our presentation.

• Journal of Information Display
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• v.7 no.3
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• pp.27-30
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• 2006

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

• Electrical & Electronic Materials
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• v.7 no.5
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• pp.376-382
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• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.