• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.31-38
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• 2010

This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1664-1671
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• 2016

This paper presents the analysis of the gate-source voltage of the gallium nitride high electronic mobility transistor (GaN HEMT) in the half bridge structure focused on the mutual effects of two switching operation. Especially low side gate-source voltage is analyzed mathematically according to the high side switch turn-on and turn-off operation. Moreover, the influence of each gate resistance and parasitic component on the switching characteristic of other side switch is investigated, and the formula, simulation and experimental results are compared with theoretical data.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.577-595
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• 2017

${\bullet}$ Silicon Carbide (SiC) had excellent material properties as the base material for next generation of power semiconductor. In developing SiC MOSFET, gate oxide reliability issues had to be first overcome before commercial application. Besides, a high and stable gate-source voltage threshold $V_{GS(th)}$ is also an important parameter for operation robustness. SiC MOSFET with such characteristics can directly use existing high-speed IGBT gate driver IC's. ${\bullet}$ The linear voltage drop characteristics of SiC MOSFET will bring lower conduction loss averaged over full AC cycle compared to similarly rate IGBT. Lower switching loss enable higher switching frequency. Using package with auxiliary source terminal for gate driving will further reduce switching losses. Dynamic characteristics can fully controlled by simple gate resistors. ${\bullet}$ The low switching losses characteristics of SiC MOSFET can substantially reduce power losses in high switching frequency operation. Significant power loss reduction is also possible even at low switching frequency and low switching speed. in T-type 3-level topology, SiC MOSFET solution enable three times higher switching freqeuncy at same efficiency.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.195-197
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• 1998

The large scale industry needs high voltage converters. Therefore series connection of power semiconductor devices is necessary. It is important to prevent a device induced the overvoltage above ratings by proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by control the slope of collector voltage under series connected IGBT turn-off transient. The propose gate control scheme limits the overvoltage by sensing the collector voltage and controlling the gate signal actively. The new series connected IGBT gate driver is made and its validity is verified by the experimental results for series connected IGBT circuit.

• Journal of Power Electronics
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• v.14 no.2
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• ETRI Journal
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• v.26 no.1
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• pp.7-13
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• 2004

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1117-1126
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• 2017

The main contribution of this paper is the use of sensorless active diodes to generate the gate signals for a three-phase boost-rectifier with a self-powered control scheme. The sensorless operation is achieved making use of the gate control signals generated by the active diode schemes on each of the switching devices using a pulse width half-controlled boost rectifier modulation technique (PWM-HCBR). The proposed scheme synchronizes the gate control signals with a three phase voltage supply. Autonomous operation is obtained making use of the output DC bus to feed the control circuitry, the active diodes and the driver circuitry. The three-phase boost-rectifier is supplied by a three-phase permanent magnet electric generator powered by a solar concentrator dish with variable voltage and variable frequency conditions. Experimental results report an efficiency of up to 94.6% for 25 W and an input of 3.6 V peak per phase with 450.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.24-29
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• 2003

A 120kV/70A high voltage switch has been installed at Korea Atomic Energy Research Institute(KAERI) in Taejon to supply power with Korea Superconducting Tokamak Advanced Research(KSTAR) Neutral Beam Injection(NBI) system. NBI system requires fast cutoff of the flower supply voltage for protection of the grid when arc detected and fast turn-on the voltage for sustaining the beam current. Therefore the high voltage switch and arc current detection circuit are important part of the NBI power supply. There are much need for high voltage solid state switches in NBI system and a broad area of applications. This switch consisted of 100 series connected MOSFETs and adopted the proposed simple and reliable gate drive circuit without bias supply. Various results taken during the commissioning phase with a 100kW resistive load and NBI source arc shown. This paper presents the detailed design of 120kV/70A high voltage MOSFETs switch and simple gate drive circuit. Problems with the high voltage switch and gate driver during thefabrication and test and solutions are also presented.

• Journal of IKEEE
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• v.24 no.1
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• pp.132-139
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• 2020

The ionizer module used in this air cleaner supplies high voltages of 3.5KV / -4KV to the discharge electrode HV+ / HV- using a winding transformer to generate positive and negative ions by electric field radiation of carbon fiber brush. The ionizer module circuit using the existing MCU has the disadvantage of large PCB size and expensive price, and the gate driver chip using the existing ring oscillator has oscillation period sensitive to PVT (Process-Voltage-Temperature) fluctuation and there is risk of fire or electric shock because there is no fault detection function by short circuit of HV+ and GND as well as HV- and GND. Therefore, in this paper, even though PVT fluctuates, by using 7-bit binary up counter, HV+ voltage reaches the target voltage by adjusting oscillation period. And an HV+ short fault detection circuit for detecting a short circuit between HV+ and GND, an HV- short fault detection circuit for detecting a short circuit between HV- and GND, and an OVP (Over-Voltage Protection) for detecting that HV+ rises above an overvoltage are newly proposed.