• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.23-27
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.

• Korea-Australia Rheology Journal
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• v.12 no.1
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• pp.83-92
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• 2000

In resin transfer molding (RTM) process, preplaced fiber mat is set up in a mold and thermoset resin is injected into the mold. An important interest in RTM process is to minimize cycle time without sacrificing part quality or increasing cost. In this study, the numerical simulation and optimization process in filling stage were conducted in order to determine the optimum gate locations. Control volume finite element method (CVFEM) was used in this numerical analysis with the coordinate transformation method to analyze the complex 3-dimensional structure. Experiments were performed to monitor the flow front to validate simulation results. The results of numerical simulation predicted well the experimental results with every single, simultaneous and sequential injection procedure. We performed the optimization analysis for the sequential injection procedure to minimize fill time. The complex geometry of an automobile bumper core was chosen. Genetic algorithm was used in order to determine the optimum gate locations with regard to 3-step sequential injection case. These results could provide the information of the optimum gate locations in each injection step and could predict fill time and flow front.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.789-794
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• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of the Society of Naval Architects of Korea
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• v.45 no.6
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• pp.611-619
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• 2008

In most shipyards Floating Dock-gate System is adapted for dry docks. For the safe launching of ships in dry docks, smooth operation of dock-gate must be guaranteed. So it is very important to grasp its behavior in waves for securing the high productivity and the safety of workers. Its seakeeping ability was estimated numerically at the floating conditions and the free roll decay and the seakeeping model tests of dock-gate was carried out with bilge-keels of 3 different widths which have a scale of 1 to 20. More than 20% decrease of roll motion was observed in irregular beam seas by applying a bilge-keel system to the dock-gate that is long and narrow.

• 한국방재학회:학술대회논문집
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• 2008.02a
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• pp.791-794
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• 2008

The transport and dispersion of pollutants in natural river is a principal issue in intake station management. To study the pollutant transport in natural rivers, the effect of meandering and confluence of tributary on mixing process have to analyzed. The objective of this study is to simulate the mixing and transport of pollutants for operating water gate of Nakdong Estuary Barrage around the intake station. Mulgeum intake station being used as drinking water sources for Pusan. The flow around the intake station is influenced by operating water gate of Nakdong Estuary Barrage which is located downstream. The water gate system includes ten individual gates. The minor gate is usually opened according to elevation of the sea. When the river flow increases, the main water gate is opened. Daepo stream, tributary of the Nakdong river, is on opposite side of the intake station. The pollutants from Daepo stream often flows into the intake station acoording to the flow pattern. In this study, based on this simulation results, proper water gate operation which can minimize negative impact will be provided.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.54-61
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• 2011

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.