• Progress in Superconductivity
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• 제4권2호
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.331-341
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• 2013

In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

• 전자공학회논문지C
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• 제35C권1호
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• 한국전기전자재료학회논문지
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• 제18권2호
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• pp.120-124
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• 2005

In this work, MOS capacitors were used to study the electrical properties of Mo gate electrode deposited on ZrO$_2$. The workfunctions of Mo gate extracted from C-V curves were appropriate for PMOS. Thermal stability of Mo metal was investigated by analyzing the variations of workfunction and EOT(effective oxide thickness) after 600, 700, and 800 $^{\circ}C$ RTA(rapid thermal annealing). It was found that Mo gate was stable up to 800 $^{\circ}C$ with underlying ZrO$_2$. The resistivities of Mo were 35$\mu$Ω$.$cm∼ 75$\mu$Ω$.$cm. These values are lower than those of heavily doped polysilicon. Based on these measurements, it can be concluded that Mo metal gate with ZrO$_2$ gate insulator is an excellent gate material for PMOS.

• 한국수소및신에너지학회논문집
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• 제15권4호
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• pp.317-323
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• 2004

We fabricated a MISFET using Pd/NiCr gate for the detecting of hydrogen gas in the air and investigated its electrical characteristics. To improve stability and high concenntration sensitivity and remove the blister generated by the penetration of hydrogen atoms Pd/NiCr catalyst gate metal are used as dual gate. To reduce the gate drift voltage caused by the inflow of hydrogen, the gate insulators of sensing and reference FFET were constructed with double insulation layers of silicon dioxide and silicon nitride. The hydrogen response of MISFET were amplified with the difference of gate voltages of both MISFET. To minimize the drift and the noise, we used a OP177 operational amplifier. The sensitivity of the Pd/NiCr gate MISFET was lower than that of Pd/Pt gate MISFET, but it showed good stability and ability to detect high concentration hydrogen up to 1000ppm.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2002년도 춘계학술대회논문집
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• pp.13-19
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• 2002

In inner harbour of Inchon Port, there are two lock gates (50KT, 10KT) which have two gates per lock gate in inner/outer sides except a gate in inner harbour side 7f 10KT. Due to the lack of the fore-mentioned gate, the use of 10KT lock gate Is suspended in every 3 years for regular maintenance. Now an additional gate is under construction in order to improve the efficiency of the 10KT lock gate. This paper will be aimed to evaluate the operational utilization levels of lock gates in present and future. The present operational utilization levels of lock gates are 0.2119 in 10KT lock gate, 0.2051 in 50KT lock gate which were considered the 46.5 closed days every 3 years for 10KT regular maintenance. The levels are estimated to 0.2246(10KT), 0.2539(50KT) in 2006 and 0.2241(10KT), 0.2560(50KT) in 2011. The levels of 50KT lock gate are evaluated to be more rapidly increased up to 24.5% in 2011.

• 동국한의학연구소논문집
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• 제2권1호
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• pp.1-17
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• 1993

This study is to know the concept and function of Vital Gate. The results are summarized as follows, 1. Vital Gate is the original of life, which is essential to life. 2. A physiological function of Vital Gate controls the physiological activity of the whole body through Triple Heater. 3. It is said that a partial establishment of Vital Gate is the concept of Hwang Jeong(黃庭) as the central point of the body. 4. It is effective that a clinical application of Vital Gate uses on the basis of Zoagyuyeum(左歸飮) and Woogyuyeum(右歸陰). 5. Fire of the Vital Gate means a original activity of life-activity and is different from the concept of the fire of Pericardium as a substitute for King Fire. 6. It is said that to explain the essence of Vital Gate in relation of kidney is to say the generative function. According to the above results, Vital Gate is understood as the control of physiological activity of the whole body as the original point of life-activity.