• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.718-720
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• 1999

This paper describes a charge pump PLL architecture which achieves high frequency operation and fast acquisition. This architecture employs multi-phase frequency detector comprised of precharge type phase frequency detector and conventional phase frequency detector. Operation frequency is increased by using precharge type phase frequency detector when the phase difference is small and acquisition time is shortened by using conventional phase frequency detector and increased charge pump current when the phase difference is large. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 694MHz at 3.0V and faster acquisition were achieved by simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1163-1171
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• 2007

In this paper, the design techniques required to design heterodyned OPLL such as frequency-phase deference detector, loop filter and phase noise of semiconductor laser are presented. Through the experiments with the calculated parameters, we confirmed that the frequency-phase difference detector simply develops an error component that is proportional to the frequency-phase difference between heterodyned optical signals. The achieved frequency-phase locking range of the input laser diode frequency is around ${\pm}150MHz$. This paper describes the details of the designed as well as experimental results.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.102-105
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3117-3119
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• 1999

In this paper, a new phase detector which can detect phase difference of variable input frequency and represent as a DC voltage is designed. The proposed phase detector has detection range from $-180^{\circ}$ to $180^{\circ}$. It is implemented by digital electronic circuit. It operates from 125 kHz to 4 MHz frequency of input signal and it's maximum phase error is $360/256^{\circ}$.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.10
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.271-274
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• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.