• Journal of Welding and Joining
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• 제26권3호
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• pp.30-36
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• 2008

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.49-56
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• 2012

최근 전자 제품의 소형화, 박형화 및 집적화에 따라 칩과 기판을 연결하는 범프의 미세화가 요구되고 있다. 그러나 범프의 미세화는 직경 감소와 UBM의 단면적 감소로 인하여 전류 밀도를 증가시켜 전기적 단락을 야기할 수 있다. 특히 범프에서 형성되는 금속간화합물과 KV의 형성은 전기적 및 기계적 특성에 큰 영향을 줄 수 있다. 따라서 본 논문에서는 유한요소해석을 이용하여 플립칩 범프의 열변형을 분석하였다. 우선 TCT의 온도조건을 통하여 플립칩 패키지의 열변형 특성을 분석한 결과, 범프의 열 변형이 시스템의 구동에 큰 영향을 미칠 수 있음을 확인하였다. 그리고 범프의 열변형 특성에 큰 영향을 미칠 것을 생각되는 IMC층의 두께와 범프의 직경을 변수로 선정하여 온도변화, 열응력 및 열변형에 대한 해석을 수행하였으며, 이를 통하여 IMC층이 범프에 영향을 미치는 원인에 대한 분석을 수행하였다.

• 마이크로전자및패키징학회지
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• 제21권2호
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• pp.37-41
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• 2014

차세대 전자 소자 기술에서 전력전달은 소자의 전력을 낮추고 발열로 인한 문제 해결을 위해서 매우 중요한 기술로 대두되고 있다. 본 연구에서는 직사각형 ABL 전력 범프를 이용한, Cu-to-Cu 플립 칩 본딩 공정의 신뢰성 문제에 대해 살펴보았다. 다이 내 범프 높이 차이는 전기도금 후 CMP 공정을 진행했을 경우 약 $0.3{\sim}0.5{\mu}m$ 이었고, CMP 공정을 진행하지 않았을 경우는 약 $1.1{\sim}1.4{\mu}m$으로 나타났다. 또한 면적이 큰 ABL 전력 범프가 입출력 범프 보다 높이가 높게 나타났다. 다이 내 범프 높이 차이로 인해 플립 칩 본딩 공정 시 misalignment 문제가 발생하였고, 이는 본딩 quality 에도 영향을 미쳤다. Cu-to-Cu 플립 칩 공정을 위해선 다이 내 범프 높이 균일도와 Cu 범프의 평탄도 조절이 매우 중요한 요소라 하겠다.

• 마이크로전자및패키징학회지
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• 제15권4호
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• pp.9-15
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• 2008

Au와 Sn을 순차적으로 도금한 Au/Sn 범프를 플립칩 본딩하여 Au-Sn 솔더 접속부를 형성 후, 미세구조와 접속저항을 분석하였다. $285^{\circ}C$에서 30초간 플립칩 본딩한 Au-Sn 솔더 접속부는 $Au_5Sn$+AuSn lamellar 구조로 이루어져 있으며, 이 시편을 $310^{\circ}C$에서 3분간 유지하여 2차 리플로우시 $Au_5Sn$+AuSn interlamellar spacing이 증가하였다. $285^{\circ}C$에서 30초간 플립칩 본딩한 Au-Sn 접속부는 15.6 $m{\Omega}$/bump의 평균 접속저항을 나타내었으며, 이 시편을 다시 $310^{\circ}C$에서 3분간 유지하여 2차 리플로우 한 Au-Sn 접속부는 15.0 $m{\Omega}$/bump의 평균 접속저항을 나타내었다.

• 한국재료학회지
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• 제17권2호
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• pp.91-95
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• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

• 대한금속재료학회지
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• 제46권5호
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• pp.310-314
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• 2008

Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

• 제어로봇시스템학회논문지
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• 제15권9호
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• pp.916-921
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• 2009

The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

• Journal of Welding and Joining
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• 제19권5호
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• pp.520-525
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• 2001

The Sn-Pb eutectic solder bump formation ($150\mu\textrm{m}$ diameter, $250\mu\textrm{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Pb deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased wish increasing time. The plating rate became constant at limiting current density. After the characteristics of Sn-Pb plating were investigated, Sn-Pb solder bumps were fabricated in optimal condition of $7A/dm^$. 4hr. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallurgy). The shear strength of Sn-Pb bump after reflow was higher than that of before reflow.

• 마이크로전자및패키징학회지
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• 제16권3호
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• pp.67-73
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• 2009

Cu pillar 범프를 사용한 플립칩 접속부는 솔더범프 접속부에 비해 칩과 기판사이의 거리를 감소시키지 않으면서 미세피치 접속이 가능하기 때문에, 특히 기생 캐패시턴스를 억제하기 위해 칩과 기판사이의 큰 거리가 요구되는 RF 패키지에서 유용한 칩 접속공정이다. 본 논문에서는 칩에는 Cu pillar 범프, 기판에는 Sn 범프를 전기도금하고 이들을 플립칩 본딩하여 Cu pillar 범프 접속부를 형성 한 후, Sn 전기도금 범프의 높이에 따른 Cu pillar 범프 접속부의 접속저항과 칩 전단하중을 측정하였다. 전기도금한 Sn 범프의 높이를 5 ${\mu}m$에서 30 ${\mu}m$로 증가시킴에 따라 Cu pillar 범프 접속부의 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 향상되었으며, 칩 전단하중이 3.8N에서 6.8N으로 증가하였다. 반면에 접속부의 종횡비는 1.3에서 0.9로 저하하였으며, 접속부의 종횡비, 접속저항 및 칩 전단하중의 변화거동으로부터 Sn 전기도금 범프의 최적 높이는 20 ${\mu}m$로 판단되었다.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.