Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Flip Chip Process for RF Packages Using Joint Structures of Cu and Sn Bumps

Cu 범프와 Sn 범프의 접속구조를 이용한 RF 패키지용 플립칩 공정

  • Choi, J.Y. (Materials Science and Engineering, Hongik University) ;
  • Kim, M.Y. (Materials Science and Engineering, Hongik University) ;
  • Lim, S.K. (Materials Science and Engineering, Hongik University) ;
  • Oh, T.S. (Materials Science and Engineering, Hongik University)
  • 최정열 (홍익대학교 신소재공학과) ;
  • 김민영 (홍익대학교 신소재공학과) ;
  • 임수겸 (홍익대학교 신소재공학과) ;
  • 오태성 (홍익대학교 신소재공학과)
  • Published : 2009.09.30
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Abstract

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

Cu pillar 범프를 사용한 플립칩 접속부는 솔더범프 접속부에 비해 칩과 기판사이의 거리를 감소시키지 않으면서 미세피치 접속이 가능하기 때문에, 특히 기생 캐패시턴스를 억제하기 위해 칩과 기판사이의 큰 거리가 요구되는 RF 패키지에서 유용한 칩 접속공정이다. 본 논문에서는 칩에는 Cu pillar 범프, 기판에는 Sn 범프를 전기도금하고 이들을 플립칩 본딩하여 Cu pillar 범프 접속부를 형성 한 후, Sn 전기도금 범프의 높이에 따른 Cu pillar 범프 접속부의 접속저항과 칩 전단하중을 측정하였다. 전기도금한 Sn 범프의 높이를 5 ${\mu}m$에서 30 ${\mu}m$로 증가시킴에 따라 Cu pillar 범프 접속부의 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 향상되었으며, 칩 전단하중이 3.8N에서 6.8N으로 증가하였다. 반면에 접속부의 종횡비는 1.3에서 0.9로 저하하였으며, 접속부의 종횡비, 접속저항 및 칩 전단하중의 변화거동으로부터 Sn 전기도금 범프의 최적 높이는 20 ${\mu}m$로 판단되었다.

Keywords

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