• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.155-159
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• 2017

The analog-to-digital converter (ADC) is an important component in various fields of sensor signal processing. This paper presents an expandable flash analog-to-digital converter (E-flash ADC) for sensor signal processing using a comparator, a subtractor, and a multiplexer (MUX). The E-flash ADC was simulated and designed in $0.35-{\mu}m$ standard complementary metal-oxide semiconductor (CMOS) technology. For operating the E-flash ADC, input voltage is supplied to the inputs of the comparator and subtractor. When the input voltage is lower than the reference voltage, it is outputted through the MUX in its original form. When it is higher than the reference voltage, the reference voltage is subtracted from the input value and the resulting voltage is outputted through the MUX. Operation of the MUX is determined by the output of the comparator. Further, the output of the comparator is a digital code. The E-flash ADC can be expanded easily.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.378-385
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• 2008

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a $0.25{\mu}m$ pure digital CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.28-35
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• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.436-439
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• 2011

본 논문은 클록 보정회로를 가진 1V 2.56-GS/s 6-bit flash analog-to-digital converter (ADC) 제안한다. 제안하는 ADC 구조에서 아날로그 블록은 단일 T/H와 2단의 프리앰프, 그리고 비교기를 사용된다. 2단의 프리앰프와 비교기의 출력에 옵셋의 크기를 줄이기 위하여 저항 평균화 기법을 적용하였다. 디지털 블록은 quasi-gray rom base 구조를 사용한다. 3입력 voting 회로로 flash ADC에서 발생하기 쉬운 bubble error를 제거하였으며, 고속 동작을 위해 단일 클록을 사용하는 TSPC F/F로 구현한다. 제안하는 flash ADC는 클록 듀티 비를 조절할 수 있는 클록 보정회로를 사용한다. 클록 보정 회로는 비교기 클록 듀티 비를 조절하여 리셋 시간과 evaluation 시간의 비율을 최적화함으로 dynamic 특성을 확보한다. 제안한 flash ADC는 1V 90nm의 CMOS 공정에서 설계되었다. Full power bandwidth인 1.2 GHz 입력에 대하여 ADC 성능을 시뮬레이션을 통해 확인하였다. 설계된 flash ADC의 면적과 전력소모는 각각 $800{\times}400\;{\mu}m^2$와 193.02mW 이다.