JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A CMOS 5-bit 5GSample/Sec Analog-to-digital Converter in 0.13um CMOS

  • Wang, I-Hsin (Graduate Institute Electronics Engineering and Department of Electrical Engineering, National Taiwan University) ;
  • Liu, Shen-Iuan (Graduate Institute Electronics Engineering and Department of Electrical Engineering, National Taiwan University)
  • Published : 2007.03.31
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Abstract

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

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References

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