• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.160-164
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• 2010

The radio frequency (RF) model of SOI FinFETs with gate length of 40 nm is verified by using a 3-dimensional (3-D) device simulator. This paper shows the equivalent circuit model which can be used in the circuit analysis simulator. The RMS modeling error of Y-parameter was calculated to be only 0.3 %.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1815-1821
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• 2006

In this paper, the subthreshold swing has been analyzed for FinFET under channel length of 20nm. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current and WKB(Wentzel-Kramers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values agree well. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as am as possible to decrease this short channel effects, and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained. Note that subthreshold swings are resultly constant at low doping concentration.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.865-868
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• 2006

In this paper, the subthreshold swing has been analyzed for double gate FinFET under channel length of 20nm. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel-Framers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.869-872
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• 2006

In this paper, the threshold voltage roll-off been analyzed for nano structure double gate FinFET. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel- framers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off Is very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.209-209
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• 2010

단위면적 당 메모리 집적도를 높이기 위해 플래시 기억소자의 크기를 줄일 때, 절연층 두께 감소에 의한 누설 전류의 발생, 단채널 효과 및 협폭 효과와 같은 문제 때문에 소자 크기의 축소가 한계에 도달하고 있다. 이러한 문제점들을 개선하기 위해 본 연구에서는 FinFET구조위에 Oxide-Nitride-Oxide (ONO) 층을 적층하여 2-비트 특성을 갖는 플래시 메모리 소자를 제안하였다. 소자의 작동전압을 크게 줄일 수 있으며 소자의 크기가 작아질 때 일어나는 단채널 효과의 문제점을 해결할 수 있는 FinFET 구조를 가진 기억소자에서 제어게이트를 제어게이트1과 제어게이트2로 나누어 독립적으로 쓰기 및 소거 동작하도록 하였다. 2-비트 동작을 위해 제어 게이트1의 게이트 절연막의 두께를 제어게이트2의 게이트 절연막의 두께보다 더 얇게 함으로써 두 제어게이트 사이의 coupling ratio를 다르게 하였다. 제어게이트1의 트랩층의 두께를 제어게이트2의 트랩층의 두께보다 크게 하여 제어게이트1의 트랩층에 더 많은 양의 전하가 포획될 수 있도록 하였다. 제안한 기억소자가 2-비트 동작하는 것을 확인 하기위하여 2차원 시뮬레이션툴인 MEDICI를 사용하여 제시한 FinFET 구조를 가진 기억소자의 전기적 특성을 시뮬레이션하였다. 시뮬레이션을 통해 얻은 2-비트에 대한 각 상태에서 각 전하 포획 층에 포획된 전하량의 비교를 통해서 coupling ratio 차이와 전하 포획층의 두께 차이로 인해 포획되는 전하량이 달라졌다. 각 상태에서 제어게이트에 읽기 전압을 인가하여 전류-전압 특성 곡선을 얻었으며, 각 상태에서의 문턱전압들이 잘 구분됨을 확인함으로써 제안한 FinFET 구조를 가진 플래시 메모리 소자가 셀 당 2-비트 동작됨을 알 수 있었다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.56-61
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• 2015

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.