• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.1-10
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• 2003

Device characteristics of the Metal-Ferroclecric-Semiconductor FET(MFSFET) are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V$_{G}$ curves generated from our MFSFET simulation exhibit the accumulation, the depletion and the inversion regions clearly. The capacitance, the subthreshold and the drain current characteristics as a function of gate bias exhibit the memory windows are 1 and 2 V, when the coercive voltages of ferroelectric are 0.5 and 1 V respectively. I$_{D}$-V$_{D}$ curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I$_{D}$-V$_{D}$ curve is 1.5, 2.7, 4.0, and 5.7 ㎃, when the gate biases are 0, 0.1, 0.2 and 0.3V respectively. As the drain current is demonstrated after time delay, PLZT(10/30/70) thin film shows excellent reliability as well as the decrease of saturation current is about 18 % after 10 years. Our simulation model is expected to be very useful in the estimation of the behaviour of MFSFET devices.T devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.570-576
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• 2007

In this study, the characteristics of metal-ferroelectric-semiconductor FET (MFSFET) device is investigated using field-dependent polarization and square-law FET models. From drain current with the gate voltage variation, when coercive voltages of ferroelectric thin film are 0.5 and 1V, the memory windows are 1 and 2V, respectively. When the gate voltages are 0, 0.1, 0.2 and 0.3V, the difference of saturation drain currents of the MFSFET device at two threshold voltages in ID-VD curve are 1.5, 2.7, 4.0, and 5.7mA, respectively. As a result of the analysis for drain currents after tine lapse, which is based on the simulation for hysteresis loop and the fitting of retention properties of ferroelectric thin films such as PLZT(10/30/70), PLT(10) and PZT(30/70) thin film shows excellent reliability that the decrease of saturation current is about 18% after 10 years.

• Journal of Adhesion and Interface
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• v.22 no.3
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• pp.91-97
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• 2021

By introducing an organic interlayer on the Parylene C dielectric surface, the electrical device performances and the operating stabilities of organic field-effect transistors (OFETs) were improved. To achieve this goal, hexamethyldisilazane (HMDS) and octadecyltrichlorosilane (ODTS), as the organic interlayer materials, were used to control the surface energy of the Parylene C dielectrics. For the bare case used with the pristine Parylene C dielectrics, the field-effect mobility (μ_FET) and threshold voltage (V_th) of dinaphtho[2,3-b:2',3'-f ]thieno[3,2-b]- thiophene (DNTT) FET devices were measured at 0.12 cm²V^-1s^-1 and - 5.23 V, respectively. On the other hand, the OFET devices with HMDS- and ODTS-modified cases showed the improved μ_FET values of 0.32 and 0.34 cm²V^-1s^-1, respectively. More important point is that the μ_FET and V_th of the DNTT FET device with the ODTS-modified Parylene C dielectric presented the smallest changes during a repeated measurement of 1000 times, implying that it has the most stable operating stability. The results could be meaned that the organic interlayer, especially ODTS, effectively covers the Parylene C dielectric surface with alkyl chains and reduces the charge trapping at the interface region between active layer and dielectric, thereby improving the electrical operating stability.

• Vacuum Magazine
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• v.3 no.1
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• pp.16-21
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• 2016

FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.57-62
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• 1993

In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.488-489
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different substrate temperature. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2031-2036
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• 2022

Energetic particle strikes the device and induces data corruption in the configuration memory (CRAM), causing errors and even malfunctions in a system on chip (SoC). Software-based fault injection is a convenient way to assess device performance. In this paper, dynamic partial reconfiguration (DPR) is adopted to make fault injection on a Xilinx 16 nm FinFET Ultrascale+ MPSoC. And the reconfiguration module implements the Sobel and Gaussian image filtering, respectively. Fault injections are executed on the static and reconfiguration modules' bitstreams, respectively. Another contribution is that the failure modes and effects analysis (FMEA) method is applied to evaluate the system reliability, according to the obtained injection results. This paper proposes a software-based solution to estimate programmable device vulnerability.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.30-37
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• 2014

In this paper, the compact model for FinFET gate resistance is developed. Based on the FinFET geometry and material, the value of the gate resistance is extracted by Y-parameter analysis using 3D device simulator, Sentaurus. By dividing the gate resistance into horizontal and vertical components, the proposed gate resistance model captures the non-linear characteristics. The proposed compact model reflects the realistic gate structure which has two different materials (Tungsten, TiN) stacked. Using the proposed model, the number of fins for the minimum gate resistance can be proposed based on the variation of gate geometrical parameters. The proposed gate resistance model is implemented in BSIM-CMG. A ring-oscillator is designed, and its delay performance is compared with and without gate resistance.