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http://dx.doi.org/10.5573/ieie.2014.51.8.030

FinFET Gate Resistance Modeling and Optimization  

Lee, SoonCheol (College of Information and Communication Engineering, Sungkyunkwan University)
Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University)
Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.8, 2014 , pp. 30-37 More about this Journal
Abstract
In this paper, the compact model for FinFET gate resistance is developed. Based on the FinFET geometry and material, the value of the gate resistance is extracted by Y-parameter analysis using 3D device simulator, Sentaurus. By dividing the gate resistance into horizontal and vertical components, the proposed gate resistance model captures the non-linear characteristics. The proposed compact model reflects the realistic gate structure which has two different materials (Tungsten, TiN) stacked. Using the proposed model, the number of fins for the minimum gate resistance can be proposed based on the variation of gate geometrical parameters. The proposed gate resistance model is implemented in BSIM-CMG. A ring-oscillator is designed, and its delay performance is compared with and without gate resistance.
Keywords
FinFET; ring oscillator;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
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