• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.1-10
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• 1999

Direct extraction of FET's small signal model parameters needs predetermined parasitic elements usually obtained under forward cold FET conditionl This paper derives analytic intrinsic model for cold FET's and shows that normal cold FET condition can replace forward cold FET condition for extracting parasitic elements. Then, we track the error of hot FET's small signal model bounded by the cold FET condition and examine the validness of cold parasitic resistances by checking the existence of the error minimum.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.67-75
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• 2013

In this paper, an analytical model is presented for the source/drain parasitic resistance of FinFET. The parasitic resistance is a important part of a total resistance in FinFET because of current flow through the narrow fin. The model incorporates the contribution of contact and spreading resistances considering three-dimensional current flow. The contact resistance is modeled taking into account the current flow and parallel connection of dividing parts. The spreading resistance is modeled by difference between wide and narrow and using integral. We show excellent agreement between our model and simulation which is conducted by Raphael, 3D numerical field solver. It is possible to improve the accuracy of compact model such as BSIM-CMG using the proposed model.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.123-127
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• 2017

This paper fabricated and analyzed the image rejection mixer that uses FET's channel resistance. It can be applied for capacity 64QAM that has 50MHz~90MHz of IF band, 8.17GHz of LO frequency and 8.08~8.12GHz of RF band. When IF input power is -20dBm and LO input power is 10dBm, RF output power is obtained -33.2dBm. In this case, conversion loss is 12.9dB, the suppression of 14.3dB for LO frequency and 10.4dB for image frequency. The result of two tone test shows great IMD characteristics with 51.7dBc.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.73-78
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• 2004

In this paper, it is designed for 5.8GHz Wireless LAN sub harmonic resistive mixer. Sub harmonic resistive mixer is constituted by advantage of sub harmonic mixer and resistive mixer. Sub harmonic resistive mixers mix harmonics of LO with RF and obtain IF frequency. Therefore, it was possible to use decreasing LO frequency than conventional mixers. And, Sub harmonic resistive mixer has low IMD because of using unbiased channel resistance of GaAs FET. When LO power is 13dBm, the conversion loss of manufactured sub harmonic resistive mixer is 10.67 dB. And IIP3 of mixer is 21.5dBm.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.39-48
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• 2016

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.271-271
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• 2014

본 연구에서는 최근 다양한 전자 소자로써의 연구가 진행되고 있는 그라핀을 SiO2/Si 기판 위에 전자빔 식각(Electron-Beam Lithography)을 이용하여 후면 게이트 전극 구조의 그라핀 채널을 갖는 삼단자 소자를 형성하고 가스 유입이 가능한 진공 Probe Measurement System을 이용하여 금속 전극과 그라핀 간의 접촉저항 (Rc) 및 길이가 다른 채널저항(Rch)를 구하고, 채널 길이, 가스 유량, 온도, 게이트 전압에 따른 I-V 변화를 측정함으로써, 후면 게이트 전극 구조의 그라핀 채널을 갖는 삼단자 소자의 가스 센서로서의 가능성을 연구하였다. 후면 게이트 전극 구조의 그라핀 채널을 갖는 삼단자 소자는 전자빔 식각(Electron-Beam Lithography)에 의해 패턴을 제작하고 Evaporator를 이용하여 전극을 증착 하였다. 소자의 소스 (Source)와 드레인 (Drain)은 TLM (Transfer Length Method)패턴을 이용하여 인접한 두 개의 전극간 범위를 변화시키는 형태로 제작함으로써 소스-드레인간 채널 길이가 다르게 하였다. 이 때 전극의 크기는 가로, 세로 각각 $20{\mu}m$, $40{\mu}m$이며 전극간 간격은 $20/30/40/50/60{\mu}m$로 서로 다르게 배열 하였다. 제작된 그라핀 소자는 진공 Probe Measurement System 내에서 게이트 전압(VG)를 변화시킴으로써 VG 변화에 따른 소자의 특성을 평가하였는데, mTorr 상태의 챔버 내로 O2 가스를 주입하여 그라핀의 Dangling bond 및 Defect site에 결합 된 가스로 인한 전기적 특성의 변화를 측정하고, 이 때 가스의 유량을 50 sccm에서 500 sccm 까지 변화시킴으로써 전기적 특성 변화를 측정하여 센서 소자의 민감도를 평가하였다. 또한, 서로 다르게 배열한 소스-드레인 간의 채널 길이로 인하여 채널과의 접촉 면적에 따른 센서 소자의 민감도 또한 평가할 수 있었다. 그리고 챔버 내 온도를 77 K에서 400 K까지 변화시킴으로써 온도에 따른 소자의 작동 범위를 확인하고 소자의 온도의존성을 평가하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.2
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• pp.59-64
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• 2004

In this paper, a Cold PHEMT equivalent circuit was proposed, and it is applied to extract extrinsic resistances. By using the proposed Cold PHEMT equivalent circuit, the variation of impedance with frequency and bias were mainly emphasized. Especially, the convergence of impedance with frequency and the change in impedance with bias were carefully analyzed, which may be used for fast extraction of extrinsic resistances. The proposed extraction method demonstrated improving of small signal model accuracy than conventional extraction method.

• Journal of Adhesion and Interface
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• v.21 no.3
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• pp.86-92
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• 2020

We confirmed the effects on the device performances and the charge injection characteristics of organic field-effect transistor (OFET) by selectively differently controlling the surface energies on the contact region of the substrate where the source/drain electrodes are located and the channel region between the two electrodes. When the surface energies of the channel and contact regions were kept low and increased, respectively, the field-effect mobility of the OFET devices was 0.063 ㎠/V·s, the contact resistance was 132.2 kΩ·cm, and the subthreshold swing was 0.6 V/dec. They are the results of twice and 30 times improvements compared to the pristine FET device, respectively. As the results of analyzing the interfacial trap density according to the channel length, a major reason of the improved device performances could be anticipated that the pi-pi overlapping direction of polymer semiconductor molecules and the charge injection pathway from electrode is coincided by selective surface treatment in the contact region, which finally induces the decreases of the charge trap density in the polymer semiconducting film. The selective surface treatment method for the contact region between the electrode and the polymer semiconductor used in this study has the potential to maximize the electrical performances of organic electronics by being utilized with various existing processes to lower the interface resistance.