1 |
C. Auth et al., "A 22nm High Performance and Low Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistor, Self-Aligned Contacts and High Density MIM Capacitors", Symposium on VLSI Technology, pp. 131-132, June. 2012.
|
2 |
K. K, Choe, K. W Kwon, S. Y. Kim, "Circuit Performance Prediction of Scaled FinFET Following ITRS Roadmap based on Accurate Parasitic Compact Model", The Institute of Electronics Engineers of Korea, vol 52, pp. 33-46, Oct. 2015.
|
3 |
E. Pop, R. Dutton and K. Goodson, "Thermal Analysis of Ultra-Thin Body Device Scaling", Electron Devices Meeting, Technical Digest, IEEE International, pp. 36.6.1-36.6.4, Dec. 2003.
|
4 |
S. Kumar et al., "Self-consistent and efficient electro-thermal analysis for poly/metal gate FinFETs", IEDM Tech. Dig, pp. 1-4, Dec. 2006.
|
5 |
H. Gossner et al., "Unique ESD failure mechanism in a MuGFET technology", IEDM Tech. Dig, pp. 1-4, Dec. 2006.
|
6 |
B. M. Tenbroek, M. S. L. Lee, W. Redman-White, J. T. Bunyan, and M. J. Uren, "Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques" IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2240-2248, Dec. 1996.
DOI
|
7 |
J. H. Kim. S. Y Kim, "The Effect of Contact Boundary on Bulk Resistance in Hexagonal Shaped Source/Drain in FinFETs", International Technical Conference on Circuits Systems-Computers and Communications, pp. 366-369, June. 2015.
|
8 |
J. C. Guo, "Halo and LDD Engineering for Multiple VTH High Performance Analog CMOS Devices", IEEE Trans on Semiconductor Manufacturing, vol. 20, no. 3, pp. 313-322, Aug. 2007.
DOI
|
9 |
M. M. Frank, "High-k/metal gate innovations enabling continued CMOS scaling", 2011 Proceedings of ESSDERC, pp. 25-33, Sept. 2011.
|
10 |
S. Kolluri, K. Endo, E. Suzuki, K. Banerjee, "Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance", IEEE International Electron Devices Meeting, pp. 177-180, Dec. 2007.
|
11 |
S. Makovejev, S Olsen, J. P. Raskin "RF Extraction of Self-Heating Effects in FinFETs", IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3335-3341, Oct. 2011.
DOI
|
12 |
U. S. Kumar, V. R. Rao, "A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs", Electron Devices, IEEE Transactions on, vol. 63, pp. 280-287, Dec. 2015.
|
13 |
BSIM-CMG108.0.0 Technical Manual, Aug. 2014.
|
14 |
TCAD Sentaurus User's Guide, Synopsys.
|
15 |
P. M. Hall, "Resistance calculations for thin film patterns" Thin Solid Films, pp. 277-295, Sept. 1967.
|
16 |
Ivanov, Valentin I., and M. K. Trubetskov. Handbook of conformal mapping with computer-aided visualization. CRC press, 1994.
|
17 |
N Lu, S. J. Lee, R. A. Wachnik, "Symmetry Breaking in the Drain Current of Multi-Finger Transistors", Custom Integrated Circuits Conference IEEE, pp. 1-4, Sept. 2015.
|