• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.12 no.10
• /
• pp.4754-4773
• /
• 2018

In sensor medium access control (SMAC) protocol, sensor nodes can only access the channel in the scheduling and listening period. However, this fixed working method may generate data latency and high conflict. To solve those problems, scheduling duty in the original SMAC protocol is divided into multiple small scheduling duties (micro duty MD). By applying different micro-dispersed contention channel, sensor nodes can reduce the collision probability of the data and thereby save energy. Based on the given micro-duty, this paper presents an adaptive duty cycle (DC) and back-off algorithm, aiming at detecting the fixed duty cycle in SMAC protocol. According to the given buffer queue length, sensor nodes dynamically change the duty cycle. In the context of low duty cycle and low flow, fair binary exponential back-off (F-BEB) algorithm is applied to reduce data latency. In the context of high duty cycle and high flow, capture avoidance binary exponential back-off (CA-BEB) algorithm is used to further reduce the conflict probability for saving energy consumption. Based on the above two contexts, we propose an improved SMAC protocol, micro duty adaptive SMAC protocol (MDA-SMAC). Comparing the performance between MDA-SMAC protocol and SMAC protocol on the NS-2 simulation platform, the results show that, MDA-SMAC protocol performs better in terms of energy consumption, latency and effective throughput than SMAC protocol, especially in the condition of more crowded network traffic and more sensor nodes.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.10
• /
• pp.79-86
• /
• 2004

This paper proposes a dual band Voltage Controlled Oscillator(VCO) with a standard 0.3${\mu}{\textrm}{m}$ CMOS process to generate 1.07GHz and 2.07GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) was capable of producing a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -102.55dBc/Hz and -95.88dBc/Hz at 2MHz offset from 1.07GHz and 2.07GHz, respectively.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.605-606
• /
• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.4 no.1
• /
• pp.20-24
• /
• 2009

sensor node work limited energy. It is undesirable or impossible to replace the batteries that are depleted of energy because of characteristics of the sensor network. Due to the specific energy constrained environment, MAC design for sensor networks generally has to take energy consumption as one of its primary concerns. But in sensor networks, latency has been a key factor affecting the applicability of sensor networks to some delay-sensitive applications. Therefore, we propose MAC protocols based DSMAC in this paper. Which is able to dynamically change the sleeping and duty cycle of sensors is adjusted to adapt to packet amounts in buffer. Proposed MAC has energy efficiency and low latency, compared DSMAC.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.13-22
• /
• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37A no.11
• /
• pp.903-917
• /
• 2012

For transmitting sensed data, wireless sensor networks have been developed and researched for the improvement of energy efficiency, hence, many MAC protocols in WSN employ the duty cycle mechanism. Since the progressed development of the low power transceiver and processor let the high energy efficiency come true, the delivery of the multimedia data which occurs in area of sensor work should be needed to provide supplemental information. In this paper, we design a new scheme for massive transmission of large multimedia data where the duty cycle is used in contention based MAC protocol, for WMSN. The proposed scheme can be applied into the previous duty cycle mechanism because it provides two operation between normal operation and massive transmission operation. Measuring the buffer status of sender and the condition of current radio channel can be criteria for the decision of the above two operations. This paper shows the results of the experiment by performing the simulation. The target protocol of the experiment is X-MAC which is contention based MAC protocol for WSN. And two approaches, both X-MAC which operates only duty cycle and X-MAC which operates combined massive transmission scheme, are used for the comparative experiment.

• Journal of Internet Computing and Services
• /
• v.10 no.2
• /
• pp.161-169
• /
• 2009

The development of Wireless Multimedia Sensor Networks(WMSNs) is getting realized in accordance with the increased demands to provide multimedia data transmission service such as CCTV movie, image chapter information, audio information based on wireless sensor network. It is very important to provide the differentiated quality assurance of service. In this paper, we propose a sensor medium access control protocol based on DSMAC, which provides differentiated Quality of Service(QoS) for delay. A proposed protocol is able to reduce the delay without increasing the energy consumption by adaptively changing the duty cycle according to the buffer occupancy. Simulation results show that the new MAC protocol performs better in terms of latency than S-MAC and DSMAC.

• ETRI Journal
• /
• v.36 no.6
• /
• pp.924-930
• /
• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.58-61
• /
• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.19-27
• /
• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.