Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Dual band CMOS Voltage Controlled Oscillator of an arithmetic functionality with a 50% duty cycle buffer

50%듀티 싸이클 버퍼를 가진 산술 연산 구조의 이중 대역 CMOS 전압 제어 발진기

  • 한윤철 (삼성전자 System LSI 사업부) ;
  • 김광일 (인하대학교 전자전기공학부) ;
  • 이상철 (인하대학교 전자전기공학부) ;
  • 변기영 (인하대학교 UWB-IT 연구센터) ;
  • 윤광섭 (인하대학교 UWB-IT 연구센터)
  • Published : 2004.10.01
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Abstract

This paper proposes a dual band Voltage Controlled Oscillator(VCO) with a standard 0.3${\mu}{\textrm}{m}$ CMOS process to generate 1.07GHz and 2.07GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) was capable of producing a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -102.55dBc/Hz and -95.88dBc/Hz at 2MHz offset from 1.07GHz and 2.07GHz, respectively.

본 논문은 0.35㎛ CMOS 공정을 이용하여 1.070GHz와 2.07GHz의 주파수를 생성해내는 이중 대역 전압 제어 발진기를 제안한다. 50% 듀티 싸이클 회로와 반가산기를 가진 제안된 전압 제어 발진기는 일반적인 전압 제어 발진기의 주파수보다 두 배 높은 주파수를 생성해낼 수 있다 제안된 전압 제어 발진기의 측정 결과는 전압 제어 발진기 이득과 전력 소모가 각각 561MHz/V, 14.6mW로 나타났다. 이중 대역 전압 제어 발진기의 위상 잡음은 각각 1.07GHz와 2.07GHz로부터 2MHz 옵셋 주파수에서 -102.55dBc/Hz와 -95.88dBc/Hz로 측정되었다.

Keywords

References

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