Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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New Design of Duty Cycle Controllable CMOS Voltage-Controlled Oscillator for Low Power Systems

Duty Cycle 조정이 가능한 새로운 저전력 시스템 CMOS Voltage-Controlled Oscillator 설계

  • Cho, Won (VLSI Design Lab., Dept. of Electronic Engineering, Hallym University) ;
  • Lee, Sung-chul (VLSI Design Lab., Dept. of Electronic Engineering, Hallym University) ;
  • Moon, Gyu (VLSI Design Lab., Dept. of Electronic Engineering, Hallym University)
  • 조원 (한림대학교 반도체 설계 연구실) ;
  • 이성철 (한림대학교 반도체 설계 연구실) ;
  • 문규 (한림대학교 반도체 설계 연구실)
  • Published : 2006.06.21
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Abstract

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

Keywords