• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.279-282
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• 2005

A real-time measurement and control system was developed, This system is used for nurses at hospitals to check the residual quantity and changing time of Ringer's solution in nurses' room. Load Cell is utilized as a sensor to check the residual quantity of Ringer's solution, This Load Cell detects the physical changes of Ringer's solution and transfers electronic signal to the amplifier. Amplified analog signal is converted into digital signal by NO converter. Developed Embedded system, which computes these data with microprocess(8052) then makes it possible to monitor the residual quantity of Ringer's solution real-time on a server computer. A Checking system on Residual Quantity of Ringer's Solution Using Load cell cut costs using a simple design for a circuit

• Journal of Apiculture
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• v.34 no.1
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• pp.7-13
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• 2019

Vespid wasps (Vespa spp.) are the most noxious pests on apiculture, resulting in significant economic losses. Early monitoring and management are the first step to prevent the damages from vespid wasps. In this study, the acoustic signals from wasps and honey bees were measured by a microphone with a preamplifier and an analog-digital converter. In frequency analysis of the acoustic signals from wasps and honey bees, there were differences between the two species. While the fundamental frequency of the wasps was analyzed to be about 100 Hz with the strong harmonic frequencies, that of the honey bees was about 200~250 Hz. The 2nd harmonic signals from wasp were strongest while the fundamental ones from honey bees were. These different sound features generated by wasps or honey bees might be applied to develop the early monitoring system of the incursion of wasps to the apiary.

• Journal of the Korean Society of Clothing and Textiles
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• v.46 no.5
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• pp.723-740
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• 2022

This study aimed to develop an Arduino-based garment pressure device (APD) on the basis of using Single-Tact sensor by suggesting the reliable clothing pressure range and coefficient of selected sensors through the APD calibration process. Once the APD was validated, the pressure of the experimental men's lower body compression wears was measured using the APD and was compared to the pressure measured using the existing air-pack type pressure meter. The subjects were one mannequin and eight men in their 20's, and the trial compression wears were calf sleeves and pants. Clothing pressures were measured in hip, mid-thigh, calf, and ankle. In terms of the 99% confidence level, the experimental clothing pressure measured at the designated measuring points using the APD was considered identical to the one measured using an existing clothing pressure meter. Therefore, on the basis of the experiment results, this study demonstrated that the APD is as reliable as the existing clothing pressure meter within the pressure ranges of 0.54-16.79 kPa and 0.18-25.47 kPa as provided by the SingleTact sensor supplier's data on the basis of using an external ADC (Analog to Digital Converter) module.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.334-339
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• 2015

Terabit-per-second (Tb/s) transmission capacity for the next generation of long-haul communication networks can be achieved using multicarrier optical super-channel technology. In an elastic orthogonal frequency division multiplexing (OFDM) super-channel transmission system, demultiplexing a portion of an entire spectrum in the form of a subband with minimum power is critically required. A major obstacle to achieving this goal is the analog-to-digital converter (ADC), which is power-hungry and extremely expensive. Without a proper ADC that can work with low power, it is unrealistic to design a 100G coherent receiver suitable for a commercially deployable optical network. Discrete Fourier transform (DFT) is often seen as a primary technique for understanding partial demultiplexing, which can be attained either optically or electronically. If fairly comparable performance can be achieved with an all-optical DFT circuit, then a solution independent of data rate and modulation format can be obtained. In this paper, we investigate two distinct OFDM super-channel receiver models, based on electronic and all-optical DFT-technologies, for partial carrier demultiplexing in a multi-Tb/s transmission system. The performance comparison of the receivers is discussed in terms of bit-error-rate (BER) performance.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.11-14
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• 2003

A silicon based OELD driving circuit that has a new type of column driving method is proposed to reduce the driving circuit area. In comparison with the conventional method, latches in each column are removed and one DAC (digital-to-analog converter) drives several column lines. To make the DAC operate during a specific period for the low power consumption, a simple DESG (DAC Enable Signal Generator) circuit was devised and confirmed by the simulation.

• Journal of Korean Society for Atmospheric Environment
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• v.20 no.E2
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• pp.69-75
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• 2004

In this study, thin film gas sensor based on tin oxide was fabricated to examine its characteristics. Target gas is acetonitrile ($CH_3$CN) which is a blood simulant for the chemical warfare agent. Sensing materials are SnO$_2$ SnO$_2$/Pt, and Sn/Pt with thickness from 1000 to 3000 $\AA$. The sensor consists of a sensing electrode with inter-digit (IDT) type in front side and a heater in rear side. Resistance changes of sensing materials are monitored on real time basis using a data acquisition board with a 12-bit analog to digital converter. Sensitivities are measured at different operating temperatures also with different gas concentrations and film thickness. The high sensitivity is obtained for Sn (3000 $\AA$)/Pt (30 $\AA$) at 30$0^{\circ}C$ for 3 ppm. Response and recovery times were about 40 and 160 s, respectively. Repetition measurements showed very good results with $\pm$3% in full scale range.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.19-26
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• 2006

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.