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Design of an 1.8V 6-bit 100MS/s 5mW CMOS A/D Converter with Low Power Folding-Interpolation Techniques  

Moon Jun-Ho (Dept. of Semiconductor Science, Dongguk University)
Hwang Sang-Hoon (Dept. of Semiconductor Science, Dongguk Univeristy)
Song Min-Kyu (Dept. of Semiconductor Science, Dongguk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.8, 2006 , pp. 19-26 More about this Journal
Abstract
In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.
Keywords
ADC; Folding-Interpolation Architecture; Folder Reduction Circuit; Novel averaging technique;
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