Browse > Article

Design of Timing Register Structure for Area Optimization of High Resolution and Low Power SAR ADC  

Min, Kyung-Jik (Department of Electronic Engineering, Konkuk University)
Kim, Ju-Sung (Department of Electronic Engineering, Konkuk University)
Cho, Hoo-Hyun (Department of Electronic Engineering, Konkuk University)
Pu, Young-Gun (Department of Electronic Engineering, Konkuk University)
Hur, Jung (Department of Electronic Engineering, Konkuk University)
Lee, Kang-Yoon (Department of Electronic Engineering, Konkuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.8, 2010 , pp. 47-55 More about this Journal
Abstract
In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.
Keywords
SAR ADC; error correction logic; timing register; low power; high resolution;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Song,B., and Tompsett, F. "A 12-bit l-Msample/s Capacitor Error -Aver aging Pipelined A/D Converter" ISSCC Digest of Technical paaper, pp.226-227,. 1989.
2 Cho, Y., and Lee, S. " an 11b 70MHz 1.2 mm2 49mW 0.18um CMOS ADC with on-chip current/voltage references", IEEE Transactions on Circuit and Systems I, 52(10), Oct, 2005.
3 M. Yotsuyanagi, T. Etoh, and K. Hirata, "A 10 bit 50MHz pipelined CMOS A/D Converter with S/H," IEEE J. Solid-State Circuits, vol. SC-28, pp.293-300, March 1993.
4 R. E. Fletcher, "Analogue to digital converters," U.S. Patent 3938188. Feb. 10, 1976.
5 H. Kaneko, "Bipolar analog to digital converter with double detection of sign bit," U.S. Patent 3735392, May 22, 1973.
6 Ryu,S., Song,B., and Bacrania, K. " A 10-bit50-MS/s pipelined ADC with opamp current reuse." IEEE Journal of Solid-State Circuits, 42(3), pp.475-485.,march 2007.
7 Bang-sip Song. "A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter" IEEE J. Solid-State Circuits, Vol. SC-25, pp.1328-1338, Dec. 1990.