• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.230-233
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• 1987

A Dual Disital Phase Locked Loop is analyzeddesigned and tested. Two specific confisurations are considered generations second and thisrd order DPLL’s and it is found using a computer simulation and verified therretically . As a result of computer simulation the characteristcof designed I-Dullis better than the at of P-DPLL or C-Dull

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.2
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• pp.38-50
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• 1982

A new type of digital phase-locked loop (DPLL) called the modified digital Costas loop is proposed and analyzed. The main feature of the proposed loop is that the phase error detector of the loop has linear characteristic. This results from the use of the tan-1 (.) function in the loop. Accordingly, the DPLL can be characterized by a modulo-2$\pi$ linear difference equation. This paper is diveide into two parts. In Part I we describe the proposed system, and analyze the performance of the first-and second-order loops in the absence of noise by the Phase Plane technique. The locking ranges for the DPLL's to achieve exact locking independently of initial conditions have been obtained in closed forms. Also, the false lock and oscillation phenomena occurring under some initial conditions have been considered. These results have been verified by computer simulation. In Part ll we analyze the proposed system in the presence of noise. The steady state probability density function, mean and variance of the phase error have been obtained by solving the Chapman-Kolmogorov equation. These results will be presented in Part ll.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.478-491
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• 1987

In this paper, an all Digital Phase-Locked Loop(DPLL) has been propoed, which has reduced the phase error by using a half period sampling in order to improve the performance of the conventional DPLL which tracks the phase of incoming sinusoidal signal once per cycle for the Positive Going Zero crossing(PGZC) of the signal. The proposed DPLL tracks the phase of input signal twice per cycle with two samplers for the PGZC. So the loop has a half reduction of the steady state phase error fluctuation ranges without decreasing the lock-range in a whole, comparing with that of the conventional DPLL. Also, it has been known that the proposed loop is rapidly locked to input signal for the same valves of phase differenc between sucessive samples and quantization level. The analytic results of the proposed loop have been verified by computer simulation for the practically requeired conditions.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.497-500
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• 1987

A new concept in resolver-to-digital conversion is described, which is based on the digital phase locked loop(DPLL). This converter receives phase modulation and converts it into digital form using time ratio techniques. In this paper, the theories on DPLL and resolver and the design of the converter are covered.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.55-60
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• 1983

A new type of digital phase-locked loop (DPLL) that employs a multilevel quantified timing error detector (TED) is proposed and analyzed under the assumption of negligible quantizing effect and no noise. Since the timing error is quantized uniformly, the TED has a linear characteristic. From the linear characteristic of TED, a first order difference equation describing the behavior of the loop is derived. Using the system equation, the loop is analyzed mathematically for phase step and frequency step input. Desired locking condition for the loop to be locked and the lock range for the DPLL's to achieve exact locking independently of initial conditions are ob-tained. And these analyses are confirmed by timing error plane plots and computer simulation.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.7
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• pp.365-374
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• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.3
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• pp.106-113
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• 1997

In uninterruptible power supply(UPS), a high speed phase control is usually required to compensate transients in the output voltage at the instant of transfer from the ac line to the inverter when the ac line fails or backs to the ac line in case of the inverter fails. To overcome this problem, this paper pre¬sents the closed digital phase-locked loop(DPLL) techniques designed by full software with TMS320C31 digital signal processor and describes the functional operation of the proposed DPLL. Fi¬nally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.