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http://dx.doi.org/10.5573/ieek.2013.50.10.076

A DPLL with a Modified Phase Frequency Detector to Reduce Lock Time  

Hasan, Md. Tariq (Dept. of Info. and Comm. Eng., Chosun Univ.)
Choi, GoangSeog (Dept. of Info. and Comm. Eng., Chosun Univ.)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.10, 2013 , pp. 76-81 More about this Journal
Abstract
A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.
Keywords
Phase-locked loop; Lock Time; Phase Frequency Detector; Voltage Controlled Oscillator; Jitter;
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