• 제목/요약/키워드: DRIE

검색결과 70건 처리시간 0.024초

Slit Wafer Etching Process for Fine Pitch Probe Unit

  • 한명수;박일몽;한석만;고항주;김효진;신재철;김선훈;윤현우;안윤태
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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    • pp.277-277
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    • 2011
  • 디스플레이의 기술발전에 의해 대면적 고해상도의 LCD가 제작되어 왔다. 이에 따라 LCD 점등검사를 위한 Probe Unit의 기술 또한 급속도로 발전하고 있다. 고해상도에 따라 TFT LCD pad가 미세피치화 되어가고 있으며, panel의 검사를 위한 Probe 또한 30 um 이하의 초미세피치를 요구하고 있다. 따라서, 초미세 pitch의 LCD panel의 점등검사를 위한 Probe Unit의 개발이 시급하가. 본 연구에서는 30 um 이하의 미세피치의 Probe block을 위한 Slit wafer의 식각 공정 조건을 연구하였다. Si 공정에서 식각율과 식각깊이에 따른 profile angle의 목표를 설정하고, 식각조건에 따라 이 두 값의 변화를 관측하였다. 식각실험으로 Si DRIE 장비를 이용하여, chamber 압력, cycle time, gas flow, Oxygen의 조건에 따라 각각의 단면 및 표면을 SEM 관측을 통해 최적의 식각 조건을 찾고자 하였다. 식각율은 5um/min 이상, profile angle은 $90{\pm}1^{\circ}$의 값을 목표로 하였다. 이 때 최적의 식각조건은 Etching : SF6 400 sccm, 10.4 sec, passivation : C4F8 400 sccm, 4 sec의 조건이었으며, 식각공정의 Coil power는 2,600 W이었다. 이러한 조건의 공정으로 6 inch Si wafer에 공정한 결과 균일한 식각율 및 profile angle 값을 보였으며, oxygen gas를 미량 유입함으로써 식각율이 균일해짐을 알 수 있었다. 결론적으로 최적의 Slit wafer 식각 조건을 확립함으로써 Probe Unit을 위한 Pin 삽입공정 또한 수율 향상이 기대된다.

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파우더와 솔더를 이용한 저비용 비아홀 채움 공정 (Low Cost Via-Hole Filling Process Using Powder and Solder)

  • 홍표환;공대영;남재우;이종현;조찬섭;김봉환
    • 센서학회지
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    • 제22권2호
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    • pp.130-135
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    • 2013
  • This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

도마뱀 인공섬모 구조물의 접착 특성에 금속코팅이 미치는 영향 (Effects of Metal Coatings on Adhesive Characteristics of Gecko-like Micro Structures)

  • 김규혜;안태창;황희윤
    • 대한기계학회논문집A
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    • 제39권11호
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    • pp.1099-1103
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    • 2015
  • 자연계에 존재하는 다양한 생명체 중 몇몇은 벽이나 천장을 자유자재로 걸어다닌다. 이러한 생명체 중 대표적으로 Gecko는 발가락 표피에 수십억개의 주걱모양의 나노헤어를 가지고 있으며, 이러한 구조로 인하여 높은 접착력을 가진다. 본 연구에서는, 도마뱀 발바닥 섬모와 같은 미세 마이크로 구조물에 금속코팅을 하여 접착특성을 향상시키는 것을 제안한다. 도마뱀 모방 인공섬모 구조물을 DRIE공법으로 준비된 몰드를 이용하여 PDMS로 제조하였다. 그리고, 인공섬모의 금속 코팅은 플라즈마 스퍼터링을 사용하여 수행하였다. 접착력과 내구성은 실험을 유리에 반복 접착 실험으로 평가 하였다. 접착성 및 내구성 실험을 통하여 인공섬모 구조물에 금속코팅이 미치는 영향에 대해 관찰하였다.

웨이퍼 레벨 공정이 가능한 2축 수직 콤 구동 방식 마이크로미러 (Wafer-Level Fabrication of a Two-Axis Micromirror Driven by the Vertical Comb Drive)

  • 김민수;유병욱;진주영;전진아;;박재형;김용권
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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    • pp.148-149
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    • 2007
  • We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

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3차원 실장용 TSV의 펄스전류 파형을 이용한 고속 Cu도금 충전 (High Speed Cu Filling Into TSV by Pulsed Current for 3 Dimensional Chip Stacking)

  • 김인락;박준규;추용철;정재필
    • 대한금속재료학회지
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    • 제48권7호
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    • pp.667-673
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    • 2010
  • Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

3차원 Si칩 실장을 위한 효과적인 Cu 충전 방법 (Effective Cu Filling Method to TSV for 3-dimensional Si Chip Stacking)

  • 홍성철;정도현;정재필;김원중
    • 대한금속재료학회지
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    • 제50권2호
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    • pp.152-158
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    • 2012
  • The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

3차원 Si칩 실장을 위한 경사벽 TSV의 Cu 고속 충전 (High Speed Cu Filling into Tapered TSV for 3-dimensional Si Chip Stacking)

  • 김인락;홍성철;정재필
    • 대한금속재료학회지
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    • 제49권5호
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    • pp.388-394
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    • 2011
  • High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

MEMS 공정을 이용한 BGA IC 패키지용 테스트 소켓의 제작 (Fabrication of MEMS Test Socket for BGA IC Packages)

  • 김상원;조찬섭;남재우;김봉환;이종현
    • 대한전자공학회논문지SD
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    • 제47권11호
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    • pp.1-5
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    • 2010
  • 본 논문에서는 외팔보 배열 구조를 가지는 MEMS 테스트 소켓을 SOI 웨이퍼를 이용하여 개발하였다. 외팔보는 연결부분의 기계적 취약점을 보완하기 위해 모서리가 둥근 형태를 가지고 있다. 측정에 사용 된 BGA IC 패키지는 볼 수 121개, 피치가 $650{\mu}m$, 볼 직경 $300{\mu}m$, 높이 $200{\mu}m$ 을 가지고 있다. 제작된 외팔보는 길이 $350{\mu}m$, 최대 폭 $200{\mu}m$, 최소 폭 $100{\mu}m$, 두께가 $10{\mu}m$인 곡선 형태의 외팔보이다. MEMS 테스트 소켓은 lift-off 기술과 Deep RIE 기술 등의 미세전기기계시스템(MEMS) 기술로 제작되었다. MEMS 테스트 소켓은 간단한 구조와 낮은 제작비, 미세 피치, 높은 핀 수와 빠른 프로토타입을 제작할 수 있다는 장점이 있다. MEMS 테스트의 특성을 평가하기 위해 deflection에 따른 접촉힘과 금속과 팁 사이의 저항과 접촉저항을 측정하였다. 제작된 외팔보는 $90{\mu}m$ deflection에 1.3 gf의 접촉힘을 나타내었다. 신호경로저항은 $17{\Omega}$ 이하였고 접촉저항은 평균 $0.73{\Omega}$ 정도였다. 제작된 테스트 소켓은 향 후 BGA IC 패키지 테스트에 적용 가능 할 것이다.

3차원 실장용 TSV 고속 Cu 충전 및 Non-PR 범핑 (High-Speed Cu Filling into TSV and Non-PR Bumping for 3D Chip Packaging)

  • 홍성철;김원중;정재필
    • 마이크로전자및패키징학회지
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    • 제18권4호
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    • pp.49-53
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    • 2011
  • TSV(through-silicon-via)를 이용한 3차원 Si 칩 패키징 공정 중 전기 도금을 이용한 비아 홀 내 Cu 고속 충전과 범핑 공정 단순화에 관하여 연구하였다. DRIE(deep reactive ion etching)법을 이용하여 TSV를 제조하였으며, 비아홀 내벽에 $SiO_2$, Ti 및 Au 기능 박막층을 형성하였다. 전도성 금속 충전에서는 비아 홀 내 Cu 충전율을 향상시키기 위하여 PPR(periodic-pulse-reverse) 전류 파형을 인가하였으며, 범프 형성 공정에서는 리소그라피(lithography) 공정을 사용하지 않는 non-PR 범핑법으로 Sn-3.5Ag 범프를 형성하였다. 전기 도금 후, 충전된 비아의 단면 및 범프의 외형을 FESEM(field emission scanning electron microscopy)으로 관찰하였다. 그 결과, Cu 충전에서는 -9.66 $mA/cm^2$의 전류밀도에서 60분간의 도금으로 비아 입구의 도금층 과성장에 의한 결함이 발생하였고, -7.71 $mA/cm^2$에서는 비아의 중간 부분에서의 도금층 과성장에 의한 결함이 발생하였다. 또한 결함이 생성된 Cu 충전물 위에 전기 도금을 이용하여 범프를 형성한 결과, 범프의 모양이 불규칙하고, 균일도가 감소함을 나타내었다.

광중합형 수복용 복합레진의 기계적 성질에 미치는 수중침적과 Thermal Cycling의 영향 (Effect of Immersion in Water and Thermal Cycling on the Mechanical Properties of Light-cured Composite Resins)

  • 배태성;김태조;김효성
    • 대한의용생체공학회:의공학회지
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    • 제17권3호
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    • pp.327-336
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    • 1996
  • This study was performed to investigate the effec% of immersion in water and thermal cycling on the mechanical peoperties of light cured restorative composite resins. Five commerically available light-cured composite resins(Photo Clearfil A : CA, Lite-Fil A . LF, Clearril Photo Posterior CP, Prisms AP.H.. PA, 2100 : ZH) were unto The specimens of 12 m in diameter and 0.7 m in thickness were made, and an immersion in $37^{\circ}C$ water for 7 days and a thermal cycling of 1000 cycles at 15 second dwell time each in $5^{\circ}C$ and $55^{\circ}C$ baths were performed. Biaxial flexure test was conducted using the ball-on-three-ball method at the crosshead speed of 0.5mm/min. In order to investigate the deterioration of composite resins during the thermal cycling test, Weibull analysis for the biaxial flexure strengths was done. Fracture surfaces and the surfaces before and after the thermal cycling test were examined by SEM. The highest Weibull modulus value of 10.09 after thermal cycling tests which means the lowest strength variation, was observed in the CP group, and the lowest value of 4.47 was obsered in the LF Group. Biaxial flexure strengths and Knoop hardness numbers significantly decreased due to the thermal cycling ($\textit{p}$< 0.01), however, they recovered when specimens were drie4 The highest biaxial flexure strength of 125.65MPa was observed in the ZH group after the thermal cycling test, and the lowest value of 64.86MPa was observed in the CA group. Biaxial flexure strengths of ZH and CP groups were higher than those of PA, CF, and CA groups after thermal cycling test($\textit{p}$< 0.05). Knoop hardness numbers of CP group after the thermal cycling test was the highest(95.47 $\pm$ 7.35kg/$mm^2$) among the samples, while that of CA group was the lowest(30.73 $\pm$ 2.58kg/$mm^2$). Knoop hardness numbers showed the significant differences between the CP group and others after the thermal cycling test(($\textit{p}$< 0.05). Fracture surfaces showed that the composite resin failure developed along the matrix resin and the filler/resin interface region, and the cracks propagated in the conical shape from the maximum tensile stress zone.

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