• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4B
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• pp.349-359
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• 2009

In this paper, we propose a stereo-video transmission method for reduction of delay and maximization of 3D effect. Conventional multimedia synchronization algorithms were designed to achieve minimum delay and synchronize multiple video and audio streams, however, they could not be effective for 3D video transmission. In this paper, we proposed a synchronization algorithm by considering the minimum error of time difference between streams for 3D effect. The minimum error of time difference for 3D effect was derived based on a 3D subjective quality test. We compute display time of the delivered videos within the allowed time-difference and the video are displayed according to the display time. To evaluate the performance of the proposed algorithm, we implemented a real-time video communication system and subjective quality test has been conducted with the proposed system. We found that video quality displayed by the proposed system. We found that video quality displayed by the proposed algorithm ranks 'good' and 'excellent' in the DMOS (Differential Mean Opinion Score) scale, based on the MOS (Mean Opinion Score) test.

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Journal of Korea Multimedia Society
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• v.5 no.4
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• pp.405-414
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• 2002

In this paper, we propose a new objective speech quality measure using noise masking threshold for speech quality assessment of mobile telephone network environments, and verify the effectiveness of the proposed method through the experiments. For such a purpose, well known objective speech quality measures such as BSD and PSQM are first evaluated for digital mobile telephone network environments. However, these conventional methods does not have good performance under mobile networks environments compared to literary results. To be mote effective objective speech quality measure under mobile telephone environments, the proposed method employs human psychoacoustic masking effect. The DMOS, instead of MOS, is used as a subjective speech quality measure for performance evaluation. The performance comparison are carried out with speech data collected from digital mobile telephone environments. As results, the proposed measure have and average 4% higher performance, in terms of correlation, than existing objective speech quality measures such as BSD and PSQM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.371-374
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• 2015

This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Journal of IKEEE
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• v.11 no.4
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• pp.247-251
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• 2007

The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because there is no JFET resistance. But because of the electric field concentration in the corner of the gate edge, the breakdown voltage decreases. This paper is about the new structure to effectively improve the Vce(sat) voltage without breakdown voltage drop in 1700V NPT type recessed gate IGBT with p floating shielding layer. For the fabrication of the recessed gate IGBT with p floating shielding layer, it is necessary to perform the only one implant step for the shielding layer. Analysis on the Breakdown voltage shows the improved values compared to the conventional recessed gate IGBT structures. The result shows the improvement on Breakdown voltage without worsening other characteristics of the device. The electrical characteristics were studied by MEDICI simulation results.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.250-253
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• 2009

This paper presents NR (No Reference) Quality assessment method for IPTV or mobile IPTV. Because No Reference quality assessment method does not access the original signal so it is suitable for the real-time streaming service. Our proposed method use decoding parameters, such as quantization parameter, motion vector, and packet loss as a major network parameter. To evaluate performance of the proposed algorithm, we carried out subjective test of video quality with the ITU-T P.910 ACR (Absolute Category Rating) method and obtained the mean opinion score (MOS) value for QVGA 180 video sequence coded by H.264/AVC encoder. Experimental results show the proposed quality metric has a high correlation (84%) to subjective quality.