Browse > Article

Design of a Gate-VDD Drain-Extended PMOS ESD Power Clamp for Smart Power ICs  

Park, Jae-Young (Div. of Electronics and Computer Engineering, Hanyang University)
Kim, Dong-Jun (Div. of Electronics and Computer Engineering, Hanyang University)
Park, Sang-Gyu (Div. of Electronics and Computer Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.10, 2008 , pp. 1-6 More about this Journal
Abstract
The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).
Keywords
electrostatic discharge(EDS); gate-VDD; power clamp; latchup; Drain-Extended MOS;
Citations & Related Records
연도 인용수 순위
  • Reference
1 최진영, 임주섭, "소자 시뮬레이션을 이용한 ESD 보호용 NMOS 트랜지스터의 항복특성 분석", 대한전자공학회 논문지 제34권 D편 제11호, pp. 907-917, 1997
2 J.-H. Lee, J.-R. Shih, C.-S.Tang, K.-C. Liu, Y.-H.Wu, R.-Y. Shiue, T.-C. Ong, Y.-K. Peng, and J.-T. Yue, "Novel ESD protection structure with embedded SCR LDMOS for smart power technology," in Proc. IEEE Int. Reliability Physics Symp., pp. 156-161, 2002
3 Ming-Dou Ker and Kun-Hsien Lin, "The Impact of Low-Holding-Voltage Issue in High-Voltage CMOS Technology and the Design of Latchup-Free Power-Rail ESD Clamp Circuit for LCD Driver ICs," IEEE Jounal of Solid-State Circuits, vol. 40, no. 8, pp.1751-1759, Aug. 2005   DOI   ScienceOn
4 G.Meneghesso, N.Novembre, E.Zanoni, L.Sponton, L.Cerati and G.Croce, "Optimization of ESD protection structures suitable for BCD6 smart power technology," microelectronics reliability, vol. 43, pp1589-1594, 2003   DOI   ScienceOn
5 최진영, 송광섭, "HBM ESD 현상의 혼합모드 과도해석", 대한전자공학회논문지 제38권 SD편 제1호 pp. 1-12, 2001
6 V. De Heyn, G. Groeseneken, B. Keppens, M. Natarajan, L. Vacaresse, and G. Gallopyn, "Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage," in Proc. IEEE Int. Reliability Physics Symp., pp. 253-258, 2001
7 E. Chwastek, "A new method for assessing the susceptibility of CMOS integrated circuits to latch-up: The system-transient technique," in Proc. EOS/ESD Symp., pp. 149-155, 1989
8 G. Croce1, A. Andreini , L. Cerati1, G. Meneghesso, and L. Sponton, Analog Circuit Design, Netherlands:Kluwer Academic publishers, pp169-206, 2003
9 홍성모, 원태영, "CMOS 회로의 ESD에 대한 신뢰성 문제 및 보호대책", 대한전자공학회 논문지 제30권 A편 12호 pp. 1068-1077, 1993
10 R. Lewis and J. Minor, "Simulation of a system level transient-induced latchup event," in Proc. EOS/ESD Symp., pp. 193-199, 1994
11 L.Sponton, L.Cerati, G.Croce, G.Mura, S.Podda, M.Vanzi, G.Meneghesso, and E.Zanoni, "ESD Protection structures for 20V and 40V power supply suitable for BCD6 smart power technology," microelectronics reliability, vol. 42, pp1303-1306, 2002   DOI   ScienceOn
12 김흥식, 송한정, 김기홍, 최민성, 최승철, "출력단 ESD 보호회로의 설계 및 그 전기적 특성에 관한 연구", 대한전자공학회논문지 제29권 A편 제11호, pp. 1066-1074, 1992
13 M.P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker, and W. Fichtner, "Analysis of lateral DMOS power devices under ESD stress conditions," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2128-2137, Nov. 2000   DOI   ScienceOn
14 C. Duvvury, F. Carvajal, C. Jones, and D. Briggs, "Lateral DMOS design for ESD robustness," in IEDM Tech. Dig., pp. 375-378, 1997