• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.6
• /
• pp.546-551
• /
• 2002

In this paper, a triple controlled type DDFS-driven PLL frequency synthesizer with reduced complexity is used to show its applications for broadband wireless communication systems by frequency synthesis control. Since the proposed DDFS-driven PLL synthesizer is very simplified to use only phase accumulator in DDFS, it improves the switching speed and power consumption than the conventional DDFS-driven PLL frequency synthesizer. It is appropriate for applications with requirements of broadband, low-power consumption and high switching speed, since the proposed synthesizer can cover a wide range of frequency bands by the triple frequency control parameters. Method and results of frequency control parameters assignment are shown for the several frequency bands applications such as GSM, IMT-2000, Bluetooth and PCS system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.2
• /
• pp.104-110
• /
• 2003

A new direct digital frequency synthesizer (DDFS) is proposed. The DDFS uses a new ROM compression method that divides each ROM in the conventional DDFS into two ROMs (a quantization ROM and an error ROM). The total size of the ROMs in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 78 is achieved for a DDFS with 12bit output data. A DDFS with 12bit output data for sine function was implemented in a 0.35${\mu}{\textrm}{m}$ CMOS technology. The power dissipation is 9.56㎽ at 100MHz with 3.3V and the maximum operating clock frequency is 330MHz.

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.334-337
• /
• 2001

In this paper we implemented DDFS and gam-phase dectector which use output of DDFS or any sinusoidal signal input to broaden the usability of DDFS. DDFS is composed of a 32 bits phase accumulator, phase increment registers, ROM and several registers for controlling the operations. It generates the digital data for sine wave up to the half of the clock frequency. To reduce the ROM size and increase the speed, we adopt the algorithms based on Taylor's series expansion method. Data at sparse phase intervals are stored in ROM and sine data between intervals are calculated in hardware. Function of Gain-Phase Extraction consists of sine lookup of DDFS and the optimized multipliers.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3235-3245
• /
• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2004.11a
• /
• pp.431-431
• /
• 2004

• The Journal of the Acoustical Society of Korea
• /
• v.18 no.5
• /
• pp.52-57
• /
• 1999

It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.8
• /
• pp.1283-1291
• /
• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.36-43
• /
• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.

• Journal of the Institute of Convergence Signal Processing
• /
• v.12 no.4
• /
• pp.291-297
• /
• 2011

In this paper, the differential quantized method and the parallel method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed And we design the DDFS by FPGA The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). Also we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction and we can design the DDFS generating the high frequency.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.3
• /
• pp.41-51
• /
• 1997

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.