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A Direct Digital Frequency Synthesizer Using Quantization ROM And Error ROM  

양병도 (한국과학기술 전자전산학과)
성기혁 (한국과학기술 전자전산학과)
김영준 (한국과학기술 전자전산학과)
김이섭 (한국과학기술 전자전산학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.2, 2003 , pp. 104-110 More about this Journal
Abstract
A new direct digital frequency synthesizer (DDFS) is proposed. The DDFS uses a new ROM compression method that divides each ROM in the conventional DDFS into two ROMs (a quantization ROM and an error ROM). The total size of the ROMs in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 78 is achieved for a DDFS with 12bit output data. A DDFS with 12bit output data for sine function was implemented in a 0.35${\mu}{\textrm}{m}$ CMOS technology. The power dissipation is 9.56㎽ at 100MHz with 3.3V and the maximum operating clock frequency is 330MHz.
Keywords
frequency synthesizer; ROM;
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