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The Performance Analysis of the DDFS to drive PLL  

손종원 (부산기능대학 메카트로닉스과)
박창규 (부산기능대학 전기계측제어과)
김수욱 (부산기능대학 전기계측제어과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.6, no.8, 2002 , pp. 1283-1291 More about this Journal
Abstract
In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.
Keywords
DDFS; PLL; Q-logic; full Pipeline;
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