Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Design and Implementation of DDFS Including Gain-Phase Detector

Gain-Phase 추출 기능을 가진 FDFS의 설계 및 검증

  • Do, Jae-Chul (Dept of Electronic Engineering, Kyungpook National University) ;
  • Cho, Jun-Young (Dept of Electronic Engineering, Kyungpook National University) ;
  • Lee, Tae-Ho (Samsung Advanced Institute of Technology) ;
  • Song, Young-Suk (Dept of Electronic Engineering, Kyungpook National University) ;
  • Choi, Chang (Dept of Electronic Engineering, Kyungpook National University) ;
  • Park, Chong-Sik (Dept of Electronic Engineering, Kyungpook National University)
  • 도재철 (경북대학교 전자공학과) ;
  • 조준영 (경북대학교 전자공학과) ;
  • 이태호 (삼성종합기술원) ;
  • 송영석 (경북대학교 전자공학과) ;
  • 최창 (경북대학교 전자공학과) ;
  • 박종식 (경북대학교 전자공학과)
  • Published : 2001.11.24
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Abstract

In this paper we implemented DDFS and gam-phase dectector which use output of DDFS or any sinusoidal signal input to broaden the usability of DDFS. DDFS is composed of a 32 bits phase accumulator, phase increment registers, ROM and several registers for controlling the operations. It generates the digital data for sine wave up to the half of the clock frequency. To reduce the ROM size and increase the speed, we adopt the algorithms based on Taylor's series expansion method. Data at sparse phase intervals are stored in ROM and sine data between intervals are calculated in hardware. Function of Gain-Phase Extraction consists of sine lookup of DDFS and the optimized multipliers.

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