The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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Applications of Triple Controlled Type DDFS-driven PLL Frequency Synthesizer to Broadband Wireless Systems

3중조절 DDFS 구동 PLL 주파수 합성기의 광대역 무선 통신시스템에 응용

  • Heung-Gyoon Ryu (Dept. of Electronic Engineering and Research Institute of Computer, Information & Communication, Chungbuk National University) ;
  • Byeong-Rok An (Dept. of Electronic Engineering and Research Institute of Computer, Information & Communication, Chungbuk National University)
  • Published : 2002.07.01
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Abstract

In this paper, a triple controlled type DDFS-driven PLL frequency synthesizer with reduced complexity is used to show its applications for broadband wireless communication systems by frequency synthesis control. Since the proposed DDFS-driven PLL synthesizer is very simplified to use only phase accumulator in DDFS, it improves the switching speed and power consumption than the conventional DDFS-driven PLL frequency synthesizer. It is appropriate for applications with requirements of broadband, low-power consumption and high switching speed, since the proposed synthesizer can cover a wide range of frequency bands by the triple frequency control parameters. Method and results of frequency control parameters assignment are shown for the several frequency bands applications such as GSM, IMT-2000, Bluetooth and PCS system.

본 논문에서는, 구조를 간략히 한 3중 조절형의 DDFS 구동PLL 주파수 합성기를 이용하여 주파수 합성 조절법에 의한 광대역 무선통신시스템으로의 응용을 연구하였다. 제안된 DDFS 구동PLL주파수 합성기는 DDFS에서 위상누적기만을 이용하는 매우 단순화된 구조이므로, 기존 DDFS 구동PLL 주파수 합성기의 경우보다 스위칭 속도가 높으며, 전력소모를 개선시킨다. 그리고 이 제안된 3중 조절형 주파수 합성기는 3가지 주파수 조절 파라미터를 이용하여 넓은 대역의 주파수 범위의 동작이 가능하므로, 광대역 저전력 고속 특성을 갖는 응용에 적합하다. 주파수 조절 파라미터 할당 방법과 그의 결과를 제시하였으며, CSM, IMT-2000, Bluetooth 틴 PCS 시스템, 등 여러 주파수 대역에 응용하는 경우를 보였다.

Keywords

References

  1. Digital Techniques in Frequency Synthesis B-G. Goldberg
  2. IEEE Transactions on Consumer Electronics v.47 no.1 Design of DDFS-driven PLL Frequency Synthesizer with Reduced Complexity H. G. Ryu;Y. Y. Kim;H. M. Yu;S. B. Ryu
  3. IEE Electronics Letters Reduced Complexity Design for Triple-Tunable Frequency Synthesizer H. G. Ryu;Y. Y. Kim;H. M. Yu
  4. IEEE MTTS International v.3 A 5 to 10 GHz Low Spurious Triple Tuned Type PLL Synthesizer Driven by Frequency Converted DDS Unit K. Tajima;Y. Imai;Y. Kanagawa;K. Itoh
  5. IEEE ISSSTA '94 v.2 Fast Acquisition PLL Frequency Synthesizer with Improved N-Stage Cycle Swallower T. Saba;D. K. Park;S. Mori
  6. IEEE Transactions on Consumer Electronics v.45 no.3 PLL Synthesizer with Multi-Programmable Divider and Multi-Phase Detector Y. Sumi;S. Obote;N. Kitai;H. Ishii;R. Furuhashi https://doi.org/10.1109/30.793655
  7. Proceedings of the IEEE v.76 no.1 Fast Frequency Synthesis by PLL Using a Continuous Phase Divider D. Wulich https://doi.org/10.1109/5.3292