• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.189-195
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• 2006

The microstructure, electrical and dielectric properties, and stability against DC accelerated aging stress of the varistors, which are composed of quaternary system $ZnO-Pr_6O_{11}CoO-Cr_2O_3-based$ ceramics, were investigated for different $La_2O_3$ contents. The increase of $La_2O_3$ content led to more densified ceramics, whereas abruptly decreased the nonlinear properties by incorporating beyond 1.0mol%. The highest nonlinearity was obtained from 0.5mol% $La_2O_3$, with the nonlinear coefficient of 81.6 and the leakage current of $0.1{\mu}A$. The varistors doped with 0.5mol% $La_2O_3$ exhibited high stability, in which the variation rates of breakdown voltage, nonlinear coefficient, leakage current, dielectric constant, and dissipation factor were -1.1%, -3.7%, +100%, +1.4%, and +8.2%, respectively, for stressing state of $0.95V_{1mA}/150^{\circ}C/24h$.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.191-191
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• 2000

마이크로파 절연파괴(breakdown) 및 ECR 플라즈마를 발생시키기 위해 2.45 GHz 마그네트론을 사용하여 간편한 마이크로파 발생장치를 제작하였다. 이 장치는 KAIST-토카막에서 고온 플라즈마를 발생시킬 때 재현성이 좋은 플라즈마를 얻기 위해서 전 이온화하는데 이용된다. 장치에 사용한 마그네트론은 LG 전자의 2M213이고 출력 500W, 주파수 2.45GHz이며, 가정용 전자오븐에 사용된다. 기존의 가정용 마그네트론은 음극(cathode)과 양극(anode)사이에 걸리는 고전압이 60Hz의 주기를 갖기 때문에 약 16ms 마다 8ms동안만 주기적으로 초고주파를 발생한다. 이 마그네트론을 사용하여 연속적으로 발생되는 마이크로파를 얻기 위해서 음극과 양극사이에 개량된 회로로 리플전압이 작은 DC 고전압(5kV, 1A)을 인가하였다. 본 연구에서는 주기적으로 생성.소멸하는 ECR 프라즈마와 연속적인 ECR 플라즈마를 발생시켜 랑뮈어탐침과 광증배관(PMT)을 이용한 H$\alpha$ 방출(emission)을 측정하여 마이크로파 발생장치의 특성을 조사하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Transactions on Electrical and Electronic Materials
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• v.14 no.4
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• pp.193-198
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• 2013

The effects of additives (Cr, Nb, Dy, and Bi) on microstructure, electrical properties, dielectric characteristics, and aging behavior of $ZnO-V_2O_5-MnO_2-Co_3O_4-La_2O_3$ (ZVMCL) ceramics were systematically investigated. The phase formed in common for all ZVMCL ceramics modified with various additives consisted of ZnO grain as a main phase, and $Zn_3(VO_4)_2$ and $ZnV_2O_4$ as the secondary phases. The sintered density and average grain size were in the range of $5.4-5.54g/cm^3$ and $3.7-5.1{\mu}m$, respectively. The ZVMCL ceramics modified with Cr exhibited the highest breakdown field (6,386 V/cm) and the ZVMCL ceramics modified with Nb exhibited the lowest breakdown field (3,517 V/cm). All additives enhanced the nonlinear coefficient (${\alpha}$), by a small or large margin, in particular, additives such as Bi and Nb noticeably increased the nonlinear coefficient, with ${\alpha}=25.5$ and ${\alpha}=23$, respectively. However, on the whole, all additives did not improve the stability against a DC stress, compared with ZVMCL ceramics.

• Journal of the Korean Society of Safety
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• v.33 no.5
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• pp.15-20
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• 2018

This paper describes the fusing time characteristics of Light PVC Sheathed Circular Cord(VCTF) and Tray Frame Retardant(TFR) cables according to increased temperature under over current condition. The experimental equation will be used to determine the validity and reliability of the test results. The over current flowed 3, 5 and 10 times higher than the amount of allowable current using DC power supply with DAQ(Data Acquisition) measurement system. An infrared radiation heater, which was controlled by a variable AC auto transformer, was used to increase the temperature from room temperature to 50, 100 and 150 degrees Celsius. First, two type of cables were analyzed those with different cross-sectional areas with in the same structure and those with different structures with in the same cross-sectional areas. Then, it was determined how fusing time had been influenced according to the cross-sectional areas and different structures, respectively. The cable resistance was increased by joule heating according to increasing temperature. Therefore, the allowable current of cable is decreased. Finally, the fusing time of the cable was decreased due to increased temperatures at current flow, which were 3 times the amount of allowable current. The instantaneous breakdown was observed when current flow was 5 and 10 times over the amount of allowable current. The fusing time is directly affected by the structure of cable insulation.

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.470-475
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• 2002

The effects of the conditions of the collector formation on electrical characteristics of the packaged SiGe hetero-junction bipolar transistors (HBT) were investigated. While the DC characteristics of SiGe HBTs such as IV characteristic, forward current gain, Early voltage, and breakdown voltage were hardly changed after packaging, the AC characteristics such as $f_{\tau}\; and\; f_{max}$ were degraded severely. With the rise of the collector concentration, the break-down voltage decreased but the $f_{\tau}$ increased. Additionally, $\beta$ and $f_{\tau}$ values were kept high in the range of elevated collector current due to the increase of the critical current density for the onset of the Kirk effect. The devices As implanted before the collector deposition showed lower breakdown voltage and higher $f_{\tau}$ than the others, which seems to be originated from the As up-diffusion resulting in the thinner collector.

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.53-58
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• 2002

Electrical insulation and mechanical properties of the plasma sprayed oxide ceramic coatings were studied before and after the sealing treatment of the ceramic coatings. Plasma sprayed A1$_2$O$_3$-TiO$_2$ coating as the reference coating was sealed using three commercial sealants based on polymer. Penetration depth of the sealants to the ceramic coating was evaluated directly from the optical microscope using a fluorescent dye. It is estimated that the penetration depth of the sealants to the ceramic coating is from 0.2 to 0.5 mm depending on the sealants used. The preliminary test results with a DC puncture tester imply that the dielectric breakdown voltage mechanism of plasma sprayed ceramic coatings has been determined to be a corona mechanism. Dielectric breakdown voltage of the as-sprayed and as-ground samples have shown a linear trend with regard to the thickness showing an average dielectric strength of 20 kV/mm for the thickness scale studied. It is also shown that grinding the coating before sealing and adding fluorescent dye do not agent the penetration depth of sealants. All of the microhardness, two-body abrasive wear resistance, bond strength, and surface roughness of the ceramic coating after the sealing treatment are improved. The extent of improvement is different from the sealants used. However, three-point bending stress of the ceramic coating after the sealing treatment is decreased. This is attributed to the reduced micro-crack toughening effect since the cracks propagate easily through the lamellar of the coating without crack deflection and/or branching after the sealing treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.45-51
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• 2007

We designed and fabricated the planar graded-gap injector GaAs Gm diodes with $1.6{\mu}m$ active length for operation at 94 GHz. The fabrication of the Gunn diode is based on MESA etching, Ohmic metalization, and overlay metalization. The measured negative resistance characteristics of the graded-gap injector GaAs Gunn diodes are examined for two different device structures changing the distance between the cathode and the anode electrodes. Also, we discuss the DC results under the forward and the reverse biases concerning the role of the graded-gap injector. It is shown that the structure having the shorter distance between the cathode and the anode electrode has higher peak current, higher breakdown voltage, and lower threshold voltage than those of the larger distance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.83-88
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• 2002

To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.