• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.438-439
• /
• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.

• Korean Journal of Materials Research
• /
• v.14 no.8
• /
• pp.573-578
• /
• 2004

Newly developed silicide materials for ULSI should have the appropriate electrical property of low resistant as well as process compatibility in conventional CMOS process. We prepared $NiCoSi_x$ silicides from 15 nm-Co/15 nm-Ni/Si structure and performed contact dry etch process to confirm the dry etch stability and compatibility of $NiCoSi_x$ layers. We dry etched the photoresist/SiO/silicide/silicon patterns with $CF_4\;and\;CHF_3$ gases with varying powers from 100 to 200 W, and pressures from 45 to 65 mTorr, respectively. Polysilicon and silicon active layers without silicide were etched $0\sim316{\AA}$ during over etch time of 3min, while silicon layers with proposed $NiCoSi_x$ silicide were not etched and showed stable surfaces. Our result implies that new $NiCoSi_x$ silicides may replace the conventional silicides due to contact etch process compatibility.

• Journal of the Semiconductor & Display Technology
• /
• v.4 no.2 s.11
• /
• pp.7-10
• /
• 2005

[ $SiO_{2}$ ] or SiON is usually deposited and annealed after formation of silicide in real transistor fabrication processes. Nickel silicide and nickel silicide with Co interlayer were annealed at 650$^{\circ}C$ for 30 min with silica top layer in this study to investigate its thermal stability. SEM, XPS, and FPP(four point probe) were employed for the investigation. Nickel silicide with Co interlayer showed improved thermal stability. Co interlayer seems to play a key role to the stability of nickel silicide.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.1-9
• /
• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Journal of Information Display
• /
• v.1 no.1
• /
• pp.63-69
• /
• 2000

In order to improve both the level and the stability of electron emission, Mo and Co silicides were formed from Mo mono-layer and Ti/Co bi-layers on single crystal silicon field emitter arrays (FEAs), respectively. Using the slope of Fowler-Nordheim curve and tip radius measured from scanning electron microscopy (SEM), the effective work function of Mo and Co silicide FEAs were calculated to be 3.13 eV and 2.56 eV, respectively. Compared with silicon field emitters, Mo and Co silicide exhibited 10 and 34 times higher maximum emission current, 10 V and 46 V higher device failure voltage, and 6.1 and 4.8 times lower current fluctuation, respectively. Moreover, the emission currents of the silicide FEAs depending on vacuum level were almost the same in the range of $10^{-9}{\sim}10^{-6}$ torr. This result shows that silicide is robust in terms of anode current degradation due to the absorption of air molecules.

• Korean Journal of Materials Research
• /
• v.8 no.10
• /
• pp.912-917
• /
• 1998

화학적 산화막(SiOx)이 형성된 Si(100)기판 위에 Co-silicide의 형성과 계면 형상에 관한 연구를 하였다. 화학적 산화막은 과산화수소수(H2O2)의 인위적 처리에 의해 약 2nm을 형성시켰다. 그 위에 5nm 두께의 Co 박막을 전자빔 증착기에 의해 증착시킨 후 열처리하여 Co-silicide를 형성하였다. 화학적 산화막 위에서 Co-silicide 반응기구를 알아 보기 위해 $500^{\circ}C$-$900^{\circ}C$의 온도 범위에서 ex-situ와 in-situ 열처리를 하였다. 이와같이 형성된 Co-silicide 시편의 상형성, 표면 및 계면 형상, 그리고 화학적 조성을 XRD, SEM, TEM, 그리고 AES를 이용하여 분석하였다. 분석 결과 es-situ 열처리시 $700^{\circ}C$까지 CoSi2 상은 형성되지 않았고 Co의 응집화현상이 일어났다. $800^{\circ}C$ 열처리한 경우에는 CoSI2가 형성되었고 facet 현상이 크게 나타났으며 불연속적인 grain 들이 형성되었다. In-situ 열처리한 경우에는 저온에서 ($550 ^{\circ}C$)반응하여 Co-silicide가 형성되기 시작하였으며 $600^{\circ}C$부터는 facet에 의해 박막의 특성이 나빠지기 시작했다. $550^{\circ}C$에서 Co가 화학적 산화막 층을 통해 확산하여 균질한 Co-silicide를 형성하였다. 이와같이 형성된 균질한 실리사이드 층을 이용하여 다단계(55$0^{\circ}C$-$650^{\circ}C$-$800^{\circ}C$)열처리에 의해 균질한 다결정 CoSI2의 형성이 관찰되었다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1996.11a
• /
• pp.72-72
• /
• 1996

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.3
• /
• pp.615-620
• /
• 2008

We fabriacted thermal evaporated $10nm-Ni_{1-x}Co_x$(x=0.2, 0.6, and 0.7) films on 70 nm-thick polysilicon substrate with $0.5{\mu}m$ line width. NiCo composite silicide layers were formed by rapid thermal annealing (RTA) at the temperatures of $700^{\circ}C$ and $1000^{\circ}C$. Then, we checked the microstructure evaluation of silicide patterns. A FIB (focused ion beam) was used to micro-mill the interconnect patterns with low energy condition (30kV-10pA-2 sec). We investigated the possibility of selective removal of silicide layers. It was possible to remove low resistance silicide layer selectively with the given FIB condition for our proposed NiCo composite silicides. However, the silicides formed from $Ni_{40}Co_{60}$ and $Ni_{30}Co_{70}$ composition showed void defects in interconnect patterns. Those void defects hinder the selective milling for the NiCo composite silicides.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1069-1072
• /
• 2003

Germane-sillicide phase formation on S $i_{0.25}$G $e_{0.75}$ with Ni 100$\square$, Co 10$\square$/Ni 100$\square$ and Ni 50$\square$/Co 10$\square$/Ni 50$\square$ layer was studied by sheet resistance and Field Emission Scanning Electron Microscopy(FESEM). Thermal stability of nickel germane-silicide is found to be improved by sputtering Ni/Co/Ni on the SiGe. After annealing at 600, 650, $700^{\circ}C$, 30min., the nickel germane-silicide formed by Ni 50$\square$/Co 10$\square$/Ni 50$\square$ layer achieved a sheet resistance less than 17ohms/sq.(almost the same to the value before furnace annealing for 30min.) , while the process of the other two ways result in high sheet resistance and even sheet resistance fail due to Ge segregation.ion.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.27-28
• /
• 2007

In this paper, Ni-Co alloy was used for improvement of thermal stability of Ni silicide. The proposed Ni/Ni-Co structure exhibited wide temperature window of rapid thermal process. Sheet resistance as well as cross-sectional profile showed stable characteristics in spite of high temperature annealing up to $700^{\circ}C$ for 30min. Therefore, the proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni silicide for nano-scale CMOSFET technology.