• 한국정보통신학회논문지
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• 제1권2호
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• 전기학회논문지
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• 제60권2호
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• 한국통신학회논문지
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• 제22권3호
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• 한국정보통신학회논문지
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• 제19권5호
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• pp.1104-1109
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• 2015

디지털 콘텐츠의 급속한 발전으로 미래의 요구에 부합할 수 있는 고속의 보안 암호 알고리즘 설계는 중요하다. 본 논문에서는 기존의 수열 발생기 보다 더 높은 처리율을 갖는 자체 수축형 LM-128 합산 수열 발생기를 제안한다. 임계 클럭 조절형 LM-128의 설계하고 구현하여 더 낮은 클럭 사이클을 가져서 더 높은 키 수열 발생 속도를 증명한다. 제안된 임계 클럭 조절형 발생기는 128비트 비밀 키와 초기 벡터를 갖는 내부 상태 256비트로 구성되어진다. 128-비트의 보안 수준의 암호는 고화질 및 고품질의 디지털 콘텐츠 보안에 적합하다.

• 한국전자통신학회논문지
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• 제7권6호
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• pp.1301-1308
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• 2012

본 논문에서는 ADCL(adiabatic dynamic CMOS logic) buffer를 이용한 단열 논리회로용 AC 전원과 동기화된 저전력 클럭 발생기를 제안한다. CMOS 논리회로의 전력 손실을 줄이고 ADCL의 저전력 동작을 위해서, 논리회로의 clock 신호는 AC 전원 신호와 동기화 되어야 한다. 설계된 Schmitt trigger 회로와 ADCL buffer를 사용한 ADCL 주파수 분주기를 이용하여 AC 신호와 단열동작을 위한 clock 신호가 발생된다. 제안된 저전력 클럭 발생기의 소비전력은 3kHz와 10MHz에서 각각 1.181uW와 37.42uW으로 시뮬레이션에서 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• 한국전자통신학회논문지
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• 제10권10호
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• pp.1123-1130
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• 2015

NoC는 SoC의 IP 코어들 사이에서 통신하는 시스템으로 기존의 버스 시스템이나 크로스바 상호연결 시스템보다 월등히 향상된 성능을 제공한다. 그러나 NoC의 송신부와 수신부 사이에서 데이터 이동 시에 송신부와 수신부 사이에 발생하는 불안정 상태(metastability)는 극복하기 위하여 동기회로가 필요하다. 본 논문에서는 신호 영역 발생기, 선택 신호 발생기와 데이터 버퍼로 구성된 새로운 위상차 동기회로를 설계하였다. 불안정 상태가 없는 선택구간을 구하기 위하여 전송된 클럭을 지연하는 회로가 사용되며, 전송클럭과 지역 클럭을 비교하여 선택신호를 발생한다. 제안된 위상차 동기회로는 선택신호 값에 의하여 지역클럭의 상승 또는 하강 모서리 중의 하나를 선택하여 불안정 상태를 제거한다. 모의실험 결과는 제안된 위상차 동기회로가 전송된 클럭과 지역 클럭의 어떤 위상차에서도 잘 동작하는 것을 보여 주었다.