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http://dx.doi.org/10.6109/jkiice.2015.19.5.1104

A proposal of binary sequence generator, Threshold Clock-Controlled LM-128  

Jo, Jung-bok (Division of Computer Engineering, Dongseo University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.19, no.5, 2015 , pp. 1104-1109 More about this Journal
Abstract
Due to the rapid growth in digital contents, it is important for us to design a high speed and secure encryption algorithm which is able to comply with the existing and future needs. This paper proposes an alternative approach for self-decimated LM-128 summation sequence generator, which will generate a higher throughput if compared to the conventional generator. We design and implement a threshold clock-controlled LM-128 and prove that it has a lower clock cycle and hence giving a higher key stream generation speed. The proposed threshold clock-control LM-128 generator consists of 256 bits inner state with 128 bits secret key and initialization vector. The cipher achieves a security level of 128 bits to be adapted to the digital contents security with high definition and high quality.
Keywords
keystream; binary sequence; clock-control; LM-128;
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