• ETRI Journal
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• v.35 no.3
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• pp.386-396
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• 2013

A 10-Gbit/s wireless communication system operating at a carrier frequency of 300 GHz is presented. The modulation scheme is amplitude shift keying in incoherent mode with a high intermediate frequency (IF) of 30 GHz and a bandwidth of 20 GHz for transmitting a 10-Gbit/s baseband (BB) data signal. A single sideband transmission is implemented using a waveguide-tapered 270-GHz high-pass filter with a lower sideband rejection of around 60 dB. This paper presents an all-electronic design of a terahertz communication system, including the major modules of the BB and IF band as well as the RF modules. The wireless link shows that, aided by a clock and data recovery circuit, it can receive $2^7$-1 pseudorandom binary sequence data without error at up to 10 Gbit/s for over 1.2 m using collimating lenses, where the transmitted power is 10 ${\mu}W$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.155-167
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• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.848-855
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• 2001

본 논문에서는 GHz 대역의 고속 클럭 신호를 필요로 하는 데이터 통신 시스템 분야에 응용될 수 있는 새로운 구조의 클럭 및 데이터 복원회로를 제안하였다. 제안된 회로는 고속의 데이터 전송시 주로 사용되는 NRZ 형태의 데이터 복원에 적합한 구조로서 NRZ 데이터가 주입될 경우에 위상동기 회로에 발생하는 주요 잡음원인인 high frequency jitter를 방지하기 위한 새로운 위상 검출구조를 갖추고 있어서 보다 안정적인 클럭을 제공할 수 있다. 또 가변적인 지연시간을 갖는 delay cell을 이용한 위상검출기를 제안하여 위상 검출기가 갖는 dead zone 문제를 없애고, 항상 최적의 동작을 수행하여 빠른 동기 시간을 갖도록 하였다. Gbps급 대용량의 데이터를 복원하기 위한 클럭 생성을 목표로 하여 CMOS 0.25$\mu\textrm{m}$ 공정을 사용하여 설계한 후 그 동작을 HSPICE post-layout simulation을 통해 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of the Optical Society of Korea
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• v.20 no.5
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• pp.623-627
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• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.871-880
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• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.