JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

  • Kim, Jong-Hoon (Pohang University of Science and Technology Dept. of Electrical Engineering) ;
  • Lim, Ji-Hoon (Pohang University of Science and Technology Dept. of Electrical Engineering) ;
  • Kim, Byungsub (Pohang University of Science and Technology Dept. of Electrical Engineering) ;
  • Sim, Jae-Yoon (Pohang University of Science and Technology Dept. of Electrical Engineering) ;
  • Park, Hong-June (Pohang University of Science and Technology Dept. of Electrical Engineering)
  • Received : 2014.10.02
  • Accepted : 2014.12.29
  • Published : 2015.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

Keywords

References

  1. T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J.Mason, W. Rhee, H. Ainspan, B. Parker, and M. Beakes, "A 6.4 Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, pp. 2633-2645, Dec. 2005.
  2. M. Meghelli, S. Rylov, J. Bulzacchelli, W. Rhee, A. Rylyakov, H.Ainspan, B. Parker, M. Beakes, A. Chung, T. Beukema, P. Pepeljugoski, L. Shan, Y. Kwark, S. Gowda, and D. Friedman, "A 10 Gb/s 5- Tap-DFE/4-Tap-FFE transceiver in 90 nm CMOS," in IEEE Int.Solid-State Circuits Conf. Dig. Tech. Papers, pp. 80-81, Feb. 2006.
  3. R. Payne , et al., "A 6.25-Gb/s Binary Transceiver in $0.13-{\mu}m$ CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels," IEEE J. Solid-State Circuits, vol. 40, pp. 2646-2657, Dec. 2005 https://doi.org/10.1109/JSSC.2005.856583
  4. V. Balan, J. Caroselli, J. G. Chern, C. Chow, R. Dadi, C. Desai, L.Fang, D. Hsu, P. Joshi, H. Kimura, C. Y. Liu, T. W. Pan, R. Park, C.You, Y. Zeng, E. Zhang, and F. Zhong, "A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization," IEEE J.Solid-State Circuits, vol. 40, no. 9, pp. 1957-1967, Sep. 2005. https://doi.org/10.1109/JSSC.2005.848180
  5. H.-J. Chi, at al., "A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface," IEEE J.Solid-State Circuits, vol. 46, no.9, pp.897-910, Septl. 2011.
  6. K. Krishna et al., "A multigigabit backplane transceiver core in 0.13-um CMOS with a powerefficient equalization architecture," IEEE J. Solid- State Circuits, vol. 40, no. 12, pp. 2658-2666, Dec.2005. https://doi.org/10.1109/JSSC.2005.856574
  7. J.-S. Choi, M.-S. Hwang, and D.-K. Jeong, "A 0.18 _m CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method," IEEE J. Solid-State Circuits, pp.419-425, Mar. 2004.
  8. C.-F. Liao et al., "A 40 Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery," IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2492-2502, Nov. 2008. https://doi.org/10.1109/JSSC.2008.2005535
  9. S. Gondi and B. Razavi, "Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sep. 2007. https://doi.org/10.1109/JSSC.2007.903076
  10. S. Gondi, et al., "A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications," ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2005.
  11. J. Lee, "A 20-Gbps adaptive equalizer in $0.13-{\mu}m$ CMOS technology," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep. 2006. https://doi.org/10.1109/JSSC.2006.880629
  12. H. Uchiki et al., "A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude," ISSCC Dig. Tech. Papers, pp. 104-106, Feb. 2008.
  13. W.S. Kim, et al., "A 5.4Gb/s Adaptive Equalizer Using Asynchronous-Sampling Histograms," ISSCC Dig. Tech. Papers, pp. 358-359, Feb. 2011.
  14. E-Hung Chen et al., "Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BERBased Metric," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2144-2156, Sep. 2008. https://doi.org/10.1109/JSSC.2008.2001871
  15. W.-T.Beyene, "The Design of Continuous-Time Linear Equalizers Using Model Order Reduction Techniques," IEEE-EPEP, pp.187-190, Oct. 2008.
  16. M.-S. Hwang, "5-Gb/s $0.25-{\mu}m$ CMOS jittertolerant variable-interval oversampling clock data recovery circuit," IEEE J. Solid-State Circuits, vol. 37, no.12, pp.1822-1830, Dec. 2002 https://doi.org/10.1109/JSSC.2002.804342
  17. B. Analui, A. Rylyakov, S. Rylov, M. Meghelli, and A. Hajimiri, "A 10 Gb/s eye-opening monitor in 0.13 um CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 332-333.
  18. B. Analui, A. Rylyakov, S. Rylov, M. Meghelli, and A. Hajimiri, "A 10-Gb/s two-dimensional eyeopening monitor in $0.13-{\mu}m$ standard CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2689-2699, Dec. 2005. https://doi.org/10.1109/JSSC.2005.856576
  19. T. Suttorp and U. Langmann, "A 10-Gb/s CMOS serial-link receiver using eye-opening monitoring for adaptive equalization and for clock and data recovery," IEEE Custom Integrated Circuits Conf., pp. 277-280., Sep. 2007.
  20. J.-W.Moon, "An 8-Gb/s Inductorless Adaptive Passive Equalizer in $0.18-{\mu}m$ CMOS Technology," J. Semicond. Technol. ci., vol. 12, no. 4, pp. 405-410, Dec. 2012. https://doi.org/10.5573/JSTS.2012.12.4.405