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http://dx.doi.org/10.3807/JOSK.2016.20.5.623

A Power-adjustable Fully-integrated CMOS Optical Receiver for Multi-rate Applications  

Park, Kangyeob (SoC Platform Research Center, Korea Electronics Technology Institute (KETI))
Yoon, Eun-Jung (SoC Platform Research Center, Korea Electronics Technology Institute (KETI))
Oh, Won-Seok (SoC Platform Research Center, Korea Electronics Technology Institute (KETI))
Publication Information
Journal of the Optical Society of Korea / v.20, no.5, 2016 , pp. 623-627 More about this Journal
Abstract
A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10−9 bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.
Keywords
Optical receiver; Transimpedance amplifier; CMOS; Silicon; Optical interconnect;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 K. Park, B. C. Kim, B. Jung, and W.-S. Oh, “A 1-13 Gbps tunable optical receiver with supply voltage scaling,” IEICE Electron. Express 11, 20140733 (2014).   DOI
2 J. Sangirov, I. A. Ukaegbu, T.-W. Lee, M. H. Cho, and H.-H. Park, “10 Gbps Transimpedance Amplifier-Receiver for Optical Interconnects,” J. Opt. Soc. Korea 17, 44-49 (2013).   DOI
3 E. Sackinger, “The Transimpedance Limit,” IEEE Trans. Circuits Syst. I, Reg. Papers 57, 1848-1856 (2010).   DOI
4 J.-C. Seo, Y.-H. Moon, J.-H. Seo, J.-Y. Jang, T.-J. An, and J.-K. Kang, “A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO,” J. of Semicon. TECH. SCI. 13, 185 (2013).   DOI
5 C. Hermans and M. Steyaert, “A High-Speed 850-nm Optical Receiver Front-End in 0.18-μm CMOS,” IEEE J. Solid-State Circuits 41, 1606-1614 (2006).   DOI
6 S. H. Park, Q. Le, and B. Choi, “An Optical Transimpedance Amplifier Using an Inductive Buffer Stage Technique,” IEICE Trans. on Comm. E92-B, 2239-2242 (2009).   DOI
7 W.-Z. Chen, Y.-L. Cheng, and D.-S. Lin, “A 1.8V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-End,” IEEE J. of Solid-State Circuits 40, 1388-1396 (2005).   DOI
8 W.-Z. Chen and C.-H. Lu, “A 2.5 Gbps CMOS optical receiver analog front-end,” in Proc. IEEE Custom Integrated Circuits Conf. (Orlando, USA, 2002), pp. 359-362.
9 W.-S. Oh, K. Park, K.-H. Park, C.-J. Kim, and J.-K. Moon, “Design and Implementation of 10-Gb/s Optical Receiver Analog Front-End in 0.13-μm CMOS Technology,” IEICE Trans. on Electron. E93-C, 393-398 (2010).   DOI
10 J. -S. Youn, M.-J. Lee, K. Park, H. Rucker, and W.-Y. Choi, “A bandwidth adjustable integrated optical receiver with on-chip silicon avalanche photodetector,” IEICE Electron. Express 8, 404-409 (2011).   DOI
11 Y.-H. Chien, K.-L. Fu, and S.-I. Liu, “A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA,” IEEE Trans. Circuits Syst. II, Exp. Briefs 61, 845-849 (2014).   DOI
12 “VESA,” [Online]. Available: http://www.vesa.org/uncategorized/vesa-releases-displayport-1-3-standard/ [Accessed: 30-June-2016].