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http://dx.doi.org/10.5573/JSTS.2015.15.2.155

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement  

Kim, Jong-Hoon (Pohang University of Science and Technology Dept. of Electrical Engineering)
Lim, Ji-Hoon (Pohang University of Science and Technology Dept. of Electrical Engineering)
Kim, Byungsub (Pohang University of Science and Technology Dept. of Electrical Engineering)
Sim, Jae-Yoon (Pohang University of Science and Technology Dept. of Electrical Engineering)
Park, Hong-June (Pohang University of Science and Technology Dept. of Electrical Engineering)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.15, no.2, 2015 , pp. 155-167 More about this Journal
Abstract
An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.
Keywords
Adaptive equalizer; USB 3.0 high-speed receiver; jitter measurement;
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Times Cited By KSCI : 1  (Citation Analysis)
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