• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.11
• /
• pp.1-9
• /
• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.287-292
• /
• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.3
• /
• pp.193-199
• /
• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.4
• /
• pp.568-576
• /
• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.12
• /
• pp.1644-1651
• /
• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.57-63
• /
• 2009

In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.2
• /
• pp.324-328
• /
• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.188-193
• /
• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.2 s.105
• /
• pp.171-177
• /
• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.10
• /
• pp.1001-1008
• /
• 1991

.In this paper the efficient clock recovery algorithm is proposed to regenerate the manchester code at the system using the Manchester encoding scheme such as LAN. Mobile communication and digital communication systems. The proposed clock recovery circuit recovers the clock using the two times of the same original transmitted frequency can be completely recovered. The implementation of the proposed clock recovery circuit and the interpretation of test results prove the validity of the proposed algorithm.