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http://dx.doi.org/10.5370/KIEE.2012.61.2.324

Design of Wide - range Clock and Data Recovery Circuit based Dual-loop DLL using 2-step DPC  

Jung, Ki-Sang (전북대학교 전자정보공학부)
Kim, Kang-Jik (전북대학교 전자정보공학부)
Ko, Gui-Han (전북대학교 전자정보공학부)
Cho, Seong-Ik (전북대학교 전자정보 공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.61, no.2, 2012 , pp. 324-328 More about this Journal
Abstract
A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.
Keywords
2-step DPC; CDR; Dual-loop; High-speed interface;
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