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Design of Clock and Data Recovery Circuit for 622Mbps Optical Network  

Moon, Sung-Young (Department of Electronic Engineering, Hallym University)
Lee, Sung-Chul (Department of Electronic Engineering, Hallym University)
Moon, Gyu (Department of Electronic Engineering, Hallym University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.2, 2009 , pp. 57-63 More about this Journal
Abstract
In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.
Keywords
Clock and Data Recovery(CDR); Phase-Locked Loop(PLL); Burst-mode; jitter; Passive Optical Network(PON);
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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