1 |
S. Gegaert and M. Steyaert, 'A skew tolerant CMOS level-based ATM data-recovery system without PLL topology', IEEE 1997 Custom Integrated Circuits Conference, pp.453-456, 1997 IEEE
DOI
|
2 |
M. Soyuer, 'A Monolithic 2.3Gb/s 100mW Clock and Dara recovery Circuit in Silicon Bipolar Technology', IEEE J.Solid-State Circuits, Vol1.28 no.12, pp.1310-1313, 1993
DOI
ScienceOn
|
3 |
B. Razavi, 'A 2GHz 1.6mW Phase-Locked Loop', in Digest of Technical Papers of the 1996 Symposium on VLSI Circuit, pp.26-27, 1996
|
4 |
Hyeon Cheol Ki, 'An Automatic power Control Circuit suitable for High Speed Burst-mode optical transmitters', 대한전자공학회, 제43권 SD편 제11호, pp98-104, 2006
과학기술학회마을
|
5 |
박태성, 김아정, 'Technologies for Optical Transceivers for Burst Mode Operation', 전자공학회지, v.30 no.3, pp73-80, 2003년
과학기술학회마을
|
6 |
David A Johns and Ken Martin, Analog Integrated Circuit Design, wiley, 1997
|
7 |
Jae-Wook Lee, 'A Giga-bps Clock and Data Recovery Circuit with a new Phase Detector', 한국통신학회, Vo126, No.6B, pp848-855, 2001
과학기술학회마을
|
8 |
M. Banu and AE. Dunlop, "Clock recovery circuits with instantaneous locking", Electron. Lett vol.28, no.23, pp.2127-2130, 1992
DOI
ScienceOn
|