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Design and Implementation of a 40 Gb/s Clock Recovery Module Using a Phase-Locked Loop with the Clock-Hold Function  

Park Hyun (School of Electrical Engineering and Computer Science, Kyungpook National University)
Woo Dong-Sik (School of Electrical Engineering and Computer Science, Kyungpook National University)
Kim Jin-Jung (Satree Initiative)
Lim Sang-Kyu (Broadband Convergence Network Research Division, ETRI)
Kim Kang-Wook (School of Electrical Engineering and Computer Science, Kyungpook National University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.17, no.2, 2006 , pp. 171-177 More about this Journal
Abstract
A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.
Keywords
Clock and Data Recovery(CDR); 40 Gb/s; Phase-Locked Loop(PLL); Acquisition; Hold Circuit;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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