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http://dx.doi.org/10.5573/JSTS.2008.8.3.193

A Combined Clock and Data Recovery Circuit with Adaptive Cancellation of Data-Dependent Jitter  

Lee, Jin-Hee (GCT Semiconductor)
Kim, Su-Hwan (Seoul National University)
Jeong, Deog-Kyoon (Seoul National University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.8, no.3, 2008 , pp. 193-199 More about this Journal
Abstract
A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.
Keywords
Data-dependent jitter; adaptive DDJ canceller; CDR;
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