1 |
V. Stojanovic, et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," IEEE J. Solid-State Circuits, Vol.40, pp.1012-1026, Apr. 2005
DOI
ScienceOn
|
2 |
M. Sorna, et al., "A 6.4 Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp.62-63
|
3 |
J. Kim, J. Yang, S. Byun, H. Jun, J. Park, C. Conroy, and B. Kim, "A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer," IEEE J. Solid-State Circuits, Vol.40, pp.462-471, Feb. 2005
DOI
ScienceOn
|
4 |
K.-L. J. Wong, E-H. Chen, and C.-K. Ken Yang, "Modified LMS adaptation algorithm for a discretetime edge equalizer of serial I/O," in Proc. IEEE Asian Solid-State Circuits Conf., 2006, pp.387-390
|
5 |
J. F. Buckwalter, B. Analui, and A. Hajimiri, "Predicting data-dependent jitter," IEEE Trans. Circuits and Systems II: Express Briefs, Vol.51, pp.453-457, Sep. 2004
DOI
ScienceOn
|
6 |
B. Widrow and S. D. Stearns, Adaptive signal processing, Prentice Hall, 1985
|
7 |
V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, "A design procedure for all-digital phaselocked loops based on a charge-pump phase-lockedloop analogy," IEEE Trans. Circuits and Systems II: Express Briefs, Vol.54, pp.159-163, Mar. 2007
|
8 |
J. F. Buckwalter, M. Meghelli, D. J. Friedman, and A. Hajimiri, "Phase and amplitude pre-emphasis techniques for low power serial links," IEEE J. Solid-State Circuits, Vol.41, No.6, pp.1391-1399, June 2006
DOI
ScienceOn
|
9 |
J. F. Buckwalter and A. Hajimiri, "Analysis and equalization of data-dependent jitter," IEEE J. Solid-State Circuits, Vol.41, No.3, pp.607-620, Mar. 2006
DOI
ScienceOn
|
10 |
A. Kuo, T. Farahmand, N. Ou, S. Tabatabaei, and A. Ivanov, "Jitter models and measurement methods for high-speed serial interconnects," in Proc. IEEE Int. Test Conf., 2004, pp.1295-1302
|
11 |
D. A. Parker and K. K. Parhi, "Area-efficient parallel FIR digital filter implementations," in Proc. IEEE Int. Application Specific Systems, Architectures and Processors, 1996, pp.93-111
|
12 |
R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3V 20 ps time-todigital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits and Systems II: Express Briefs, Vol.53, pp.220-224, Mar. 2006
DOI
ScienceOn
|
13 |
J.-S. Choi, M.-S. Hwang, and D.-K. Jeong, "A 0.18- CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method," IEEE J. Solid-State Circuits, Vol.39, pp. 419-425, Mar. 2004
DOI
ScienceOn
|